[Intel-gfx] [PATCH 6/7] drm/i915: Don't use link_bw to select between TP1 and TP3

[Sivakumar Thulasimani]

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani at intel.com>



On 7/6/2015 5:40 PM, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> intel_dp->link_bw is going away, so consul the port_clock instead when
> choosing between TP1 and TP3.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index da036e8..46b734b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3697,8 +3697,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
>   	uint32_t DP = intel_dp->DP;
>   	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
>   
> -	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
> -	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
> +	/* Training Pattern 3 for HBR2 or 1.2 devices that support it*/
> +	if (crtc->config->port_clock == 540000 || intel_dp->use_tps3)
>   		training_pattern = DP_TRAINING_PATTERN_3;
>   
>   	/* channel equalization */

-- 
regards,
Sivakumar

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