[Intel-gfx] [PATCH v4 17/18] drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset

[Chris Wilson]

On Tue, Jul 07, 2015 at 04:15:02PM +0100, Michel Thierry wrote:
> @@ -3761,6 +3763,14 @@ i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
>  						   obj->tiling_mode,
>  						   false);
>  		size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
> +
> +		if (flags & PIN_HIGH) {
> +			search_flag = DRM_MM_SEARCH_BELOW;
> +			alloc_flag = DRM_MM_CREATE_TOP;
> +		}
> +
> +		if (flags & PIN_ZONE_4G)
> +			end = (1ULL << 32);
>  	}

This should be applied to both paths, as the PIN_HIGH is applicable to
the ggtt (keeping bits and bobs out of mappable is the plan). And with
PIN_ZONE_4G there is also no need to arbitrary impose restrictions on
applicablity (though we may never have a larger GGTT than 4G!).
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre