[Intel-gfx] [PATCH 04/10] drm/i915: CHV DDR DVFS support and another watermark rewrite

[Jani Nikula]

On Fri, 26 Jun 2015, Ville Syrjälä <ville.syrjala at linux.intel.com> wrote:
> On Fri, Jun 26, 2015 at 10:56:33AM -0700, Clint Taylor wrote:
>> On 06/24/2015 12:00 PM, ville.syrjala at linux.intel.com wrote:
>> > +	if (IS_CHERRYVIEW(dev_priv)) {
>> > +		dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
>> > +		dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
>> 
>> nit #defines for these magic values please
>
> What's the point of doing that? These values are not repeated anywhere
> else.

Documentation.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Technology Center