[Intel-gfx] [PATCH 04/10] drm/i915: CHV DDR DVFS support and another watermark rewrite

[Daniel Vetter]

On Mon, Jun 29, 2015 at 11:03:04AM +0300, Jani Nikula wrote:
> On Fri, 26 Jun 2015, Ville Syrjälä <ville.syrjala at linux.intel.com> wrote:
> > On Fri, Jun 26, 2015 at 10:56:33AM -0700, Clint Taylor wrote:
> >> On 06/24/2015 12:00 PM, ville.syrjala at linux.intel.com wrote:
> >> > +	if (IS_CHERRYVIEW(dev_priv)) {
> >> > +		dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
> >> > +		dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
> >> 
> >> nit #defines for these magic values please
> >
> > What's the point of doing that? These values are not repeated anywhere
> > else.
> 
> Documentation.

I've seend the original watermark code which did this for the massive mess
that where gen2/3/4 wm code. It was unreadable, unreviewable and because
of that had bugs. I concur with Ville here.

What we might want to do is a macro to do the "logical wm setting" -> hw
value encoding, since there's some surprising differences there between
platforms. But imo that's better done as some large-scale overall project.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch