[Intel-gfx] [PATCH 5/6] drm/i915/skl: Print out if we allow DC5/DC6 in debugfs

[Damien Lespiau]

Instead of following the traces, it's easier to just look at a debugfs
file to figure out if the driver is allowing the CSR to go into DC
states.

We cache that information into the CSR structure as we don't want to
read registers in D3 (for instance).

Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c     |  5 +++++
 drivers/gpu/drm/i915/i915_drv.h         |  1 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 20 ++++++++++++++++++++
 3 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 0af19c0..878cc7f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2623,6 +2623,11 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
 		   CSR_VERSION_MINOR(csr->version));
 
+	mutex_lock(&csr->lock);
+	seq_printf(m, "DC5 allowed: %s\n", yesno(csr->dc5_allowed));
+	seq_printf(m, "DC6 allowed: %s\n", yesno(csr->dc6_allowed));
+	mutex_unlock(&csr->lock);
+
 	if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
 		seq_printf(m, "DC3 -> DC5 count: %d\n",
 			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 64c5184..99a09dd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -751,6 +751,7 @@ struct intel_csr {
 	uint32_t mmioaddr[8];
 	uint32_t mmiodata[8];
 	enum csr_state state;
+	bool dc5_allowed, dc6_allowed;
 };
 
 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index e021b1a..bfcc990 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -491,6 +491,7 @@ static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
 
 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 {
+	struct intel_csr *csr = &dev_priv->csr;
 	uint32_t val;
 
 	assert_can_enable_dc5(dev_priv);
@@ -504,10 +505,15 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 	val |= DC_STATE_EN_UPTO_DC5;
 	I915_WRITE(DC_STATE_EN, val);
 	POSTING_READ(DC_STATE_EN);
+
+	mutex_lock(&csr->lock);
+	csr->dc5_allowed = true;
+	mutex_unlock(&csr->lock);
 }
 
 static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
 {
+	struct intel_csr *csr = &dev_priv->csr;
 	uint32_t val;
 
 	assert_can_disable_dc5(dev_priv);
@@ -518,6 +524,10 @@ static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
 	val &= ~DC_STATE_EN_UPTO_DC5;
 	I915_WRITE(DC_STATE_EN, val);
 	POSTING_READ(DC_STATE_EN);
+
+	mutex_lock(&csr->lock);
+	csr->dc5_allowed = false;
+	mutex_unlock(&csr->lock);
 }
 
 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
@@ -550,6 +560,7 @@ static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
 
 static void skl_enable_dc6(struct drm_i915_private *dev_priv)
 {
+	struct intel_csr *csr = &dev_priv->csr;
 	uint32_t val;
 
 	assert_can_enable_dc6(dev_priv);
@@ -563,10 +574,15 @@ static void skl_enable_dc6(struct drm_i915_private *dev_priv)
 	val |= DC_STATE_EN_UPTO_DC6;
 	I915_WRITE(DC_STATE_EN, val);
 	POSTING_READ(DC_STATE_EN);
+
+	mutex_lock(&csr->lock);
+	csr->dc6_allowed = true;
+	mutex_unlock(&csr->lock);
 }
 
 static void skl_disable_dc6(struct drm_i915_private *dev_priv)
 {
+	struct intel_csr *csr = &dev_priv->csr;
 	uint32_t val;
 
 	if (intel_csr_load_status_get(dev_priv) != FW_LOADED)
@@ -580,6 +596,10 @@ static void skl_disable_dc6(struct drm_i915_private *dev_priv)
 	val &= ~DC_STATE_EN_UPTO_DC6;
 	I915_WRITE(DC_STATE_EN, val);
 	POSTING_READ(DC_STATE_EN);
+
+	mutex_lock(&csr->lock);
+	csr->dc6_allowed = false;
+	mutex_unlock(&csr->lock);
 }
 
 static void skl_set_power_well(struct drm_i915_private *dev_priv,
-- 
2.1.0