[Intel-gfx] [PATCH v2 1/2] drm/i915/chv: Determine CHV slice/subslice/EU info
Jeff McGee
jeff.mcgee at intel.com
Mon Mar 2 17:33:55 PST 2015
On Fri, Feb 27, 2015 at 10:12:14PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 27, 2015 at 12:12:28PM -0800, jeff.mcgee at intel.com wrote:
> > From: Jeff McGee <jeff.mcgee at intel.com>
> >
> > Total EU was already being detected on CHV, so we just add the
> > additional info parameters. The detection method is changed to
> > be more robust in the case of subslice fusing - we don't want
> > to trust the EU fuse bits corresponding to subslices which are
> > fused-off.
> >
> > v2: Fixed subslice disable bitmasks and removed unnecessary ?
> > operation (Ville)
> >
> > Signed-off-by: Jeff McGee <jeff.mcgee at intel.com>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
This patch now also needed to support the export of CHV subslice count
to userspace (beignet).
http://lists.freedesktop.org/archives/intel-gfx/2015-March/061100.html
> > ---
> > drivers/gpu/drm/i915/i915_dma.c | 40 ++++++++++++++++++++++++++++++++++------
> > drivers/gpu/drm/i915/i915_reg.h | 2 ++
> > 2 files changed, 36 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> > index 9cbe3f5..4c33068 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -619,14 +619,42 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> >
> > /* Initialize slice/subslice/EU info */
> > if (IS_CHERRYVIEW(dev)) {
> > - u32 fuse, mask_eu;
> > + u32 fuse, eu_dis;
> >
> > fuse = I915_READ(CHV_FUSE_GT);
> > - mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
> > - CHV_FGT_EU_DIS_SS0_R1_MASK |
> > - CHV_FGT_EU_DIS_SS1_R0_MASK |
> > - CHV_FGT_EU_DIS_SS1_R1_MASK);
> > - info->eu_total = 16 - hweight32(mask_eu);
> > +
> > + info->slice_total = 1;
> > +
> > + if (!(fuse & CHV_FGT_DISABLE_SS0)) {
> > + info->subslice_per_slice++;
> > + eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
> > + CHV_FGT_EU_DIS_SS0_R1_MASK);
> > + info->eu_total += 8 - hweight32(eu_dis);
> > + }
> > +
> > + if (!(fuse & CHV_FGT_DISABLE_SS1)) {
> > + info->subslice_per_slice++;
> > + eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
> > + CHV_FGT_EU_DIS_SS1_R1_MASK);
> > + info->eu_total += 8 - hweight32(eu_dis);
> > + }
> > +
> > + info->subslice_total = info->subslice_per_slice;
> > + /*
> > + * CHV expected to always have a uniform distribution of EU
> > + * across subslices.
> > + */
> > + info->eu_per_subslice = info->subslice_total ?
> > + info->eu_total / info->subslice_total :
> > + 0;
> > + /*
> > + * CHV supports subslice power gating on devices with more than
> > + * one subslice, and supports EU power gating on devices with
> > + * more than one EU pair per subslice.
> > + */
> > + info->has_slice_pg = 0;
> > + info->has_subslice_pg = (info->subslice_total > 1);
> > + info->has_eu_pg = (info->eu_per_subslice > 2);
> > } else if (IS_SKYLAKE(dev)) {
> > const int s_max = 3, ss_max = 4, eu_max = 8;
> > int s, ss;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index e0a525c..ed84603 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1510,6 +1510,8 @@ enum skl_disp_power_wells {
> >
> > /* Fuse readout registers for GT */
> > #define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168)
> > +#define CHV_FGT_DISABLE_SS0 (1 << 10)
> > +#define CHV_FGT_DISABLE_SS1 (1 << 11)
> > #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
> > #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
> > #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
> > --
> > 2.3.0
>
> --
> Ville Syrjälä
> Intel OTC
More information about the Intel-gfx
mailing list