[Intel-gfx] All sort of cdclk stuff

[Damien Lespiau]

On Tue, Mar 31, 2015 at 02:05:35PM +0300, Mika Kahola wrote:
> This patch series rebases Ville's original cdclk patch series
> 
> http://lists.freedesktop.org/archives/intel-gfx/2014-November/055633.html
> 
> The patches include modifications to

For some reason, I haven't received all the patches listed there... and
it seems I'm not the only one:

  http://patchwork.lespiau.name/series/1293/

Patches 03 and 09 and MIA.

-- 
Damien

> 
>   drm/i915: Return more precise cdclk for gen2/3
>   drm/i915: Fix i855_get_display_clock_speed()
>   drm/i915: Fix 852GM/GMV cdclk
>   drm/i915: Add cdclk extraction for g33, 965gm and g4x
>   drm/i915: ILK cdclk seems to be 450MHz
>   drm/i915: Assume 400 MHz cdclk for the rest of gen4-7
>   drm/i915: Simplify ilk_get_aux_clock_divider()
>   drm/i915: Convert the ddi cdclk code to .get_display_clock_speed()
>   drm/i915: Warn when cdclk for the platforms is not known
>   drm/i915: Cache the current cdclk frequency in dev_priv
>   drm/i915: Use cached cdclk value
>   drm/i915: Unify ilk and hsw .get_aux_clock_divider()
>   drm/i915: Store max cdclk value in dev_priv
>   drm/i915: Don't enable IPS when pixel rate exceeds 95% of cdclk
>   drm/i915: Fix chv cdclk support
>   drm/i915: HSW cdclk change support
>   drm/i915: Add IS_BDW_ULX()
>   drm/i915: BDW cdclk change support
>   drm/i915: Limit CHV max cdclk to 320 MHz
>   drm/i915: Combined VLV, HSW, and BDW global pipe conf into single function
>             'intel_modeset_global_pipes()'
> 
> -- 
> Mika Kahola, Intel OTC
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