[Intel-gfx] [PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[Sonika Jindal]

BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.

v2: Adding clock in bxt_clk_div struct and then look for the entry with
required rate (Ville)

Signed-off-by: Sonika Jindal <sonika.jindal at intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |   45 +++++++++++++++++++++-----------------
 drivers/gpu/drm/i915/intel_dp.c  |    7 +++++-
 2 files changed, 31 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9c1e74a..7b9d226 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1327,6 +1327,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
 
 /* bxt clock parameters */
 struct bxt_clk_div {
+	int clock;
 	uint32_t p1;
 	uint32_t p2;
 	uint32_t m2_int;
@@ -1342,13 +1343,13 @@ struct bxt_clk_div {
 
 /* pre-calculated values for DP linkrates */
 static struct bxt_clk_div bxt_dp_clk_val[7] = {
-	/* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
-	/* 270 */ {4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
-	/* 540 */ {2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
-	/* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
-	/* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
-	/* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
-	/* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
+	{162000, 4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
+	{270000, 4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
+	{540000, 2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
+	{216000, 3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
+	{243000, 4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
+	{324000, 4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
+	{432000, 3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
 };
 
 static bool
@@ -1401,20 +1402,24 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
 			intel_encoder->type == INTEL_OUTPUT_EDP) {
 		struct drm_encoder *encoder = &intel_encoder->base;
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+		int link_rate;
+		int i;
 
-		switch (intel_dp->link_bw) {
-		case DP_LINK_BW_1_62:
-			clk_div = bxt_dp_clk_val[0];
-			break;
-		case DP_LINK_BW_2_7:
-			clk_div = bxt_dp_clk_val[1];
-			break;
-		case DP_LINK_BW_5_4:
-			clk_div = bxt_dp_clk_val[2];
-			break;
-		default:
-			clk_div = bxt_dp_clk_val[0];
-			DRM_ERROR("Unknown link rate\n");
+		/*
+		 * If edp1.4 intermediate frequency support is present, we set
+		 * link_bw to 0 and a valid rate index in rate_select.
+		 */
+		if (intel_dp->link_bw)
+			link_rate = clock;
+		else
+			link_rate = intel_dp->sink_rates[intel_dp->rate_select];
+
+		clk_div = bxt_dp_clk_val[0];
+		for (i = 0; i < 7; ++i) {
+			if (bxt_dp_clk_val[i].clock == link_rate) {
+				clk_div = bxt_dp_clk_val[i];
+				break;
+			}
 		}
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c9d50d1..e6ee7c6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -85,6 +85,8 @@ static const struct dp_link_dpll chv_dpll[] = {
 		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
 };
 
+static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
+				  324000, 432000, 540000 };
 static const int skl_rates[] = { 162000, 216000, 270000,
 				  324000, 432000, 540000 };
 static const int chv_rates[] = { 162000, 202500, 210000, 216000,
@@ -1161,7 +1163,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
 static int
 intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
 {
-	if (IS_SKYLAKE(dev)) {
+	if (IS_BROXTON(dev)) {
+		*source_rates = bxt_rates;
+		return ARRAY_SIZE(bxt_rates);
+	} else if (IS_SKYLAKE(dev)) {
 		*source_rates = skl_rates;
 		return ARRAY_SIZE(skl_rates);
 	} else if (IS_CHERRYVIEW(dev)) {
-- 
1.7.10.4