[Intel-gfx] [PATCH v4] drm/i915/chv: Set min freq to efficient frequency on chv

[Daniel Vetter]

On Sat, May 09, 2015 at 06:15:46PM +0530, deepak.s at linux.intel.com wrote:
> From: Deepak S <deepak.s at linux.intel.com>
> 
> After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
> Punit is expecting us to operate GPU between Rpe & Rp0. If we drop the
> frequency to RPn, punit is failing to change the vgg input voltage to
> minimum :(
> 
> Since Punit validates the rps range [RPe, RP0]. This patch
> removes unused cherryview_rps_min_freq function.
> 
> v2: Change commit message
> 
> v3: set min_freq before idle_freq (chris)
> 
> v4: Squash 'Remove unused rps min function' patch
> 
> Signed-off-by: Deepak S <deepak.s at linux.intel.com>
> Acked-by: Chris Wilson <chris at chris-wilson.co.uk>
> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

All three patches merged to dinq, thanks.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 21 ++-------------------
>  1 file changed, 2 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 064f11a..c229d7e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4689,24 +4689,6 @@ static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
>  	return rp1;
>  }
>  
> -static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
> -{
> -	struct drm_device *dev = dev_priv->dev;
> -	u32 val, rpn;
> -
> -	if (dev->pdev->revision >= 0x20) {
> -		val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
> -		rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
> -		       FB_GFX_FREQ_FUSE_MASK);
> -	} else { /* For pre-production hardware */
> -		val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
> -		rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) &
> -		       PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
> -	}
> -
> -	return rpn;
> -}
> -
>  static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
>  {
>  	u32 val, rp1;
> @@ -4958,7 +4940,8 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
>  			 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
>  			 dev_priv->rps.rp1_freq);
>  
> -	dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
> +	/* PUnit validated range is only [RPe, RP0] */
> +	dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
>  	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
>  			 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
>  			 dev_priv->rps.min_freq);
> -- 
> 1.9.1
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch