[Intel-gfx] [PATCH v2 05/29] drm/i915: Add dev_priv->psr_mmio_base

[Chris Wilson]

On Wed, Nov 04, 2015 at 11:19:53PM +0200, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Drop the EDP_PSR_BASE() thing, and just stick the PSR register offset
> under dev_priv, like we for DSI and GPIO for example.
> 
> TODO: could probably move a bunch of this kind of stuff into the device
> info instead...
> 
> v2: Drop the spurious whitespace change (Jani)
> 
> Reviewed-by: Jani Nikula <jani.nikula at intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d2a546a..cf0367a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1721,6 +1721,8 @@ struct drm_i915_private {
>  	/* MMIO base address for MIPI regs */
>  	uint32_t mipi_mmio_base;
>  
> +	uint32_t psr_mmio_base;

It appears I'm a bit late to the party, but is there any particular
reason why these two are in the middle of a gmbus block?

I expected that these would be added to intel_device_info (like the very
first display_mmio_offset). Has that fallen out of favour? But if not
intel_device_info, then the psr struct.

The mechanical changes lgtm.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre