[Intel-gfx] [DMC_BUGFIX_SKL_V2 1/5] drm/i915/skl: Added a check for the hardware status of csr fw before loading.

[Sunil Kamath]

On Wednesday 26 August 2015 01:36 AM, Animesh Manna wrote:
> Dmc will restore the csr program except DC9, cold boot,
> warm reset, PCI function level reset, and hibernate/suspend.
>
> intel_csr_load_program() function is used to load the firmware
> data from kernel memory to csr address space.
>
> All values of csr address space will be zero if it got reset and
> the first byte of csr program is always a non-zero if firmware
> is loaded successfuly. Based on hardware status will load the
> firmware.
>
> Without this condition check if we overwrite the firmware data the
> counters exposed for dc5/dc6 (help for debugging) will be nullified.
>
> v1: Initial version.
>
> v2: Based on review comments from Daniel,
> - Added a check to know hardware status and load the firmware if not loaded.
>
> Cc: Daniel Vetter <daniel.vetter at intel.com>
> Cc: Damien Lespiau <damien.lespiau at intel.com>
> Cc: Imre Deak <imre.deak at intel.com>
> Cc: Sunil Kamath <sunil.kamath at intel.com>
> Signed-off-by: Animesh Manna <animesh.manna at intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju at intel.com>
> ---
>   drivers/gpu/drm/i915/intel_csr.c | 9 +++++++++
>   1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index ba1ae03..682cc26 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -252,6 +252,15 @@ void intel_csr_load_program(struct drm_device *dev)
>   		return;
>   	}
>   
> +	/*
> +	 * Dmc will restore the csr the program except DC9, cold boot,
> +	 * warm reset, PCI function level reset, and hibernate/suspend.
> +	 * This condition will help to check if csr address space is reset/
> +	 * not loaded.
> +	 */
> +	if (I915_READ(CSR_PROGRAM_BASE))
> +		return;
> +
>   	mutex_lock(&dev_priv->csr_lock);
>   	fw_size = dev_priv->csr.dmc_fw_size;
>   	for (i = 0; i < fw_size; i++)

Valid fix and patch is ready for merge now.

Reviewed-by: A.Sunil Kamath <sunil.kamath at intel.com> 
<mailto:sunil.kamath at intel.com>

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