[Intel-gfx] [for-CI] no-used-pml4

[Chris Wilson]

---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 47 +++++++++++++------------------------
 drivers/gpu/drm/i915/i915_gem_gtt.h |  2 --
 2 files changed, 16 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6e158b3d3ea0..dff14343a4f8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -923,8 +923,8 @@ static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
 {
 	int i;
 
-	for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) {
-		if (WARN_ON(!ppgtt->pml4.pdps[i]))
+	for (i = 0; i < GEN8_PML4ES_PER_PML4; i++) {
+		if (ppgtt->pml4.pdps[i] == NULL)
 			continue;
 
 		gen8_ppgtt_cleanup_3lvl(&ppgtt->base, ppgtt->pml4.pdps[i]);
@@ -1061,18 +1061,17 @@ gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm,
 	uint32_t pml4e;
 
 	gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
-		if (!test_bit(pml4e, pml4->used_pml4es)) {
-			pdp = alloc_pdp(vm);
-			if (IS_ERR(pdp))
-				return PTR_ERR(pdp);
-
-			gen8_initialize_pdp(vm, pdp);
-			pml4->pdps[pml4e] = pdp;
-			trace_i915_page_directory_pointer_entry_alloc(vm,
-								      pml4e,
-								      start,
-								      GEN8_PML4E_SHIFT);
-		}
+		if (pml4->pdps[pml4e])
+			continue;
+
+		pdp = alloc_pdp(vm);
+		if (IS_ERR(pdp))
+			return PTR_ERR(pdp);
+
+		gen8_initialize_pdp(vm, pdp);
+		pml4->pdps[pml4e] = pdp;
+		trace_i915_page_directory_pointer_entry_alloc(vm, pml4e, start,
+							      GEN8_PML4E_SHIFT);
 	}
 
 	return 0;
@@ -1170,15 +1169,10 @@ static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm,
 				    uint64_t start,
 				    uint64_t length)
 {
-	DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4);
 	struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 	struct i915_page_directory_pointer *pdp;
 	uint64_t pml4e;
-	int ret = 0;
-
-	/* Do the pml4 allocations first, so we don't need to track the newly
-	 * allocated tables below the pdp */
-	bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4);
+	int ret;
 
 	/* The pagedirectory and pagetable allocations are done in the shared 3
 	 * and 4 level code. Just allocate the pdps.
@@ -1192,21 +1186,12 @@ static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm,
 
 		ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length);
 		if (ret)
-			goto err_out;
+			return ret;
 
 		gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e);
 	}
 
-	bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es,
-		  GEN8_PML4ES_PER_PML4);
-
 	return 0;
-
-err_out:
-	for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
-		gen8_ppgtt_cleanup_3lvl(vm, pml4->pdps[pml4e]);
-
-	return ret;
 }
 
 static int gen8_alloc_va_range(struct i915_address_space *vm,
@@ -1294,7 +1279,7 @@ static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
 		struct i915_page_directory_pointer *pdp;
 
 		gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
-			if (!test_bit(pml4e, pml4->used_pml4es))
+			if (pml4->pdps[pml4e] == NULL)
 				continue;
 
 			seq_printf(m, "    PML4E #%llu\n", pml4e);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 15b3f2e1c697..4fea0ef24345 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -311,8 +311,6 @@ struct i915_page_directory_pointer {
 
 struct i915_pml4 {
 	struct i915_page_dma base;
-
-	DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4);
 	struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4];
 };
 
-- 
2.8.0.rc3