[Intel-gfx] [PATCH] drm/i915: Unify VLV/CHV DPOunit clock gating disable/enable

[Ville Syrjälä]

On Mon, Apr 18, 2016 at 07:18:25PM +0300, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Check for VLV/CHV instead if !BXT when re-enabling DPOunit clock gating
> after DSI disable. That's what we checked when disabling the clock
> gating when enabling DSI.
> 
> Also use the same temporary variable name in both cases, and toss in a
> bit of dev vs. dev_priv cleanup while at it.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Anyone know why this wasn't picked up by the .fi CI?
Tomi?

> ---
>  drivers/gpu/drm/i915/intel_dsi.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 34328ddaaab5..599045359538 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -516,7 +516,6 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
>  	enum port port;
> -	u32 tmp;
>  
>  	DRM_DEBUG_KMS("\n");
>  
> @@ -535,11 +534,13 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
>  
>  	msleep(intel_dsi->panel_on_delay);
>  
> -	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> +		u32 val;
> +
>  		/* Disable DPOunit clock gating, can stall pipe */
> -		tmp = I915_READ(DSPCLK_GATE_D);
> -		tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
> -		I915_WRITE(DSPCLK_GATE_D, tmp);
> +		val = I915_READ(DSPCLK_GATE_D);
> +		val |= DPOUNIT_CLOCK_GATE_DISABLE;
> +		I915_WRITE(DSPCLK_GATE_D, val);
>  	}
>  
>  	/* put device in ready state */
> @@ -677,7 +678,7 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
>  
>  	intel_dsi_clear_device_ready(encoder);
>  
> -	if (!IS_BROXTON(dev_priv)) {
> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		u32 val;
>  
>  		val = I915_READ(DSPCLK_GATE_D);
> -- 
> 2.7.4

-- 
Ville Syrjälä
Intel OTC