[Intel-gfx] [PATCH 2/2] drm/i915: re-use computed offset bias for context pin

[Ceraolo Spurio, Daniele]

On 12/24/2016 2:12 AM, Chris Wilson wrote:
> On Fri, Dec 23, 2016 at 03:56:22PM -0800, daniele.ceraolospurio at intel.com wrote:
>> From: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
>>
>> The context has to obey the same offset requirements as the ring,
>> so we can re-use the same bias value we computed for the ring instead of
>> unconditionally using GUC_WOPCM_TOP.
>>
>> Suggested-by: Chris Wilson <chris at chris-wilson.co.uk>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
>> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Both
> Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
>
> Applied and pushed. Thanks for digging in to find the root cause. We
> could relax the 4096 offset for bdw+ I think, or maybe only gen6/gen7
> had enough coverage in the wild to hit the hole.
> -Chris
>

Thanks for the review :-)
We still need your patch to avoid putting any guc related object above
0xFEE00000 to fix the other side of the issue, are you planning a respin
of that?

Thanks,
Daniele