[Intel-gfx] [PATCH 123/190] drm/i915: Mark unmappable GGTT entries as PIN_HIGH

[Chris Wilson]

We allocate a few objects into the GGTT that we never need to access via
the mappable aperture (such as contexts, status pages). We can request
that these are bound high in the VM to increase the amount of mappable
aperture available.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem_context.c |  4 ++--
 drivers/gpu/drm/i915/intel_lrc.c        |  3 ++-
 drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +++++++++----
 3 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 9250a7405807..c54c17944796 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -389,7 +389,7 @@ int i915_gem_context_init(struct drm_device *dev)
 		 * context.
 		 */
 		ret = i915_gem_object_ggtt_pin(ctx->legacy_hw_ctx.rcs_state,
-					       NULL, 0, alignment, 0);
+					       NULL, 0, alignment, PIN_HIGH);
 		if (ret) {
 			DRM_ERROR("Failed to pinned default global context (error %d)\n",
 				  ret);
@@ -677,7 +677,7 @@ static int do_switch(struct drm_i915_gem_request *req)
 	if (engine->id == RCS) {
 		u32 alignment = get_context_alignment(engine->dev);
 		ret = i915_gem_object_ggtt_pin(to->legacy_hw_ctx.rcs_state,
-					       NULL, 0, alignment, 0);
+					       NULL, 0, alignment, PIN_HIGH);
 		if (ret)
 			return ret;
 	}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 86fa41770ff1..206311b55e71 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -583,7 +583,8 @@ static int intel_lr_context_pin(struct intel_context *ctx,
 	ctx_obj = ctx->engine[engine->id].state;
 	ret = i915_gem_object_ggtt_pin(ctx_obj, NULL,
 				       0, GEN8_LR_CONTEXT_ALIGN,
-				       PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
+				       PIN_OFFSET_BIAS | GUC_WOPCM_TOP |
+				       PIN_HIGH);
 	if (ret)
 		goto err;
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ba3631d216fe..6db7f93a3c1d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -649,7 +649,8 @@ intel_init_pipe_control(struct intel_engine_cs *ring)
 	if (ret)
 		goto err_unref;
 
-	ret = i915_gem_object_ggtt_pin(ring->scratch.obj, NULL, 0, 4096, 0);
+	ret = i915_gem_object_ggtt_pin(ring->scratch.obj, NULL,
+				       0, 4096, PIN_HIGH);
 	if (ret)
 		goto err_unref;
 
@@ -1891,7 +1892,9 @@ int intel_ring_map(struct intel_ring *ring)
 	int ret;
 
 	if (HAS_LLC(ring->engine->i915) && !obj->stolen) {
-		ret = i915_gem_object_ggtt_pin(obj, NULL, 0, PAGE_SIZE, 0);
+		ret = i915_gem_object_ggtt_pin(obj, NULL,
+					       0, PAGE_SIZE,
+					       PIN_HIGH);
 		if (ret)
 			return ret;
 
@@ -1906,7 +1909,8 @@ int intel_ring_map(struct intel_ring *ring)
 			goto unpin;
 		}
 	} else {
-		ret = i915_gem_object_ggtt_pin(obj, NULL, 0, PAGE_SIZE,
+		ret = i915_gem_object_ggtt_pin(obj, NULL,
+					       0, PAGE_SIZE,
 					       PIN_MAPPABLE);
 		if (ret)
 			return ret;
@@ -2505,7 +2509,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
 			} else {
 				i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 				ret = i915_gem_object_ggtt_pin(obj, NULL,
-							       0, 0, 0);
+							       0, 0,
+							       PIN_HIGH);
 				if (ret != 0) {
 					drm_gem_object_unreference(&obj->base);
 					DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
-- 
2.7.0.rc3