[Intel-gfx] force DP lane count on Broadwell platform

[Sanchez, AdolfoX]

Hello

What PRM registers should be modified to force the source lanes to report 2 lanes maximum?
Is it enough to modify the registers DP_TP_CTL and DDI_BUF_CTL, or should any other register be modified?

Best Regards,
Adolfo Sanchez.
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