[Intel-gfx] force DP lane count on Broadwell platform

[Jani Nikula]

On Wed, 18 May 2016, "Sanchez, AdolfoX" <adolfox.sanchez at intel.com> wrote:
> What PRM registers should be modified to force the source lanes to
> report 2 lanes maximum?  Is it enough to modify the registers
> DP_TP_CTL and DDI_BUF_CTL, or should any other register be modified?

You should probably look at intel_ddi_init() in intel_ddi.c, and set
intel_dig_port->max_lanes to 2. Then it should limit the source to two
lanes wherever it's needed.

Of course, I should ask you why you need this; maybe you should be
asking a different question. ;)

BR,
Jani.



-- 
Jani Nikula, Intel Open Source Technology Center