[Intel-gfx] [PATCH 2/2] drm/i915/gtt: Mark tlbs dirty on clear

[Chris Wilson]

On Mon, Oct 31, 2016 at 05:58:15PM +0200, Mika Kuoppala wrote:
> Chris Wilson <chris at chris-wilson.co.uk> writes:
> 
> > On Mon, Oct 31, 2016 at 05:24:46PM +0200, Mika Kuoppala wrote:
> >> Now when clearing ptes can modify upper level pdp's,
> >> we need to mark them dirty so that they will be flushed
> >> correctly.
> >
> > I suppose so.
> 
> It is a bit iffy if we really do, but this way we gain symmetry
> with the alloc side.

If we assume correct behaviour on the client, no. They shouldn't be
accessing any of the removed PTE, PDE, PDPE and so now follow the stale
TLB to the old pages (now reused by the system and containing garbage ->
GPU hang or carefully crafted redirection). However, on the same basis
we fill the client address space with scratch pages, we also should
prepare for random stray access which means we need to invalidate the
TLB -- however, given that this is undefined behaviour a ncurrently
executing batch may be accessing this page illegally and see the stale
value long before a newly submitted batch flushes the TLB.

So based on that we fix predictable TLB errors (such as the prefetcher
crossing the page boundary, if it still does!) for correctly behaving
batches.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre