[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/bxt: Add MST support when do DPLL calculation (rev3)

Patchwork patchwork at emeril.freedesktop.org
Fri Feb 3 04:54:43 UTC 2017


== Series Details ==

Series: drm/i915/bxt: Add MST support when do DPLL calculation (rev3)
URL   : https://patchwork.freedesktop.org/series/17815/
State : failure

== Summary ==

Series 17815v3 drm/i915/bxt: Add MST support when do DPLL calculation
https://patchwork.freedesktop.org/api/1.0/series/17815/revisions/3/mbox/

Test kms_setmode:
        Subgroup basic-clone-single-crtc:
                pass       -> INCOMPLETE (fi-skl-6700k)

fi-bdw-5557u     total:247  pass:233  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050     total:247  pass:208  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205     total:247  pass:225  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-t5700     total:78   pass:65   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900     total:247  pass:220  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820     total:247  pass:216  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770      total:247  pass:228  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r     total:247  pass:228  dwarn:0   dfail:0   fail:0   skip:19 
fi-ivb-3520m     total:247  pass:226  dwarn:0   dfail:0   fail:0   skip:21 
fi-ivb-3770      total:247  pass:226  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u     total:247  pass:224  dwarn:0   dfail:0   fail:2   skip:21 
fi-skl-6260u     total:247  pass:234  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hq    total:247  pass:227  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k     total:207  pass:188  dwarn:0   dfail:0   fail:0   skip:18 
fi-skl-6770hq    total:247  pass:234  dwarn:0   dfail:0   fail:0   skip:13 
fi-snb-2520m     total:247  pass:216  dwarn:0   dfail:0   fail:0   skip:31 
fi-snb-2600      total:247  pass:215  dwarn:0   dfail:0   fail:0   skip:32 

0f01216949002d20b9dc6d300c82df5ffa59e9a7 drm-tip: 2017y-02m-02d-19h-49m-15s UTC integration manifest
aeeab6a drm/i915/bxt: Add MST support when do DPLL calculation

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3685/


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