[Intel-gfx] [PATCH 23/67] drm/i915/gen10: Set value of Indirect Context Offset for gen10

[Vivi, Rodrigo]

On Fri, 2017-06-02 at 10:50 +0100, Tvrtko Ursulin wrote:
> On 06/04/2017 20:15, Rodrigo Vivi wrote:
> > From: Michel Thierry <michel.thierry at intel.com>
> > 
> 
> Some commit message needed just to satisfy the form.

What about:

Indirect Context Offset Pointer has changed for Cannonlake.

INDIRECT_CTX_OFFSET[15:6] valid value for CNL is 19h per Spec.

> 
> > v2: rebased to intel_lr_indirect_ctx_offset
> > 
> > Signed-off-by: Michel Thierry <michel.thierry at intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> > ---
> >   drivers/gpu/drm/i915/intel_lrc.c | 5 +++++
> >   1 file changed, 5 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> > index f2d57b4..ac38469 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -209,6 +209,7 @@
> >   
> >   #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x17
> >   #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x26
> > +#define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x19
> >   
> >   /* Typical size of the average request (2 pipecontrols and a MI_BB) */
> >   #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
> > @@ -1787,6 +1788,10 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
> >   	default:
> >   		MISSING_CASE(INTEL_GEN(engine->i915));
> >   		/* fall through */
> > +	case 10:
> > +		indirect_ctx_offset =
> > +			GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> > +		break;
> >   	case 9:
> >   		indirect_ctx_offset =
> >   			GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> > 
> 
> After some documentation and commit log traversing to find the relevant 
> page, and with a short sentence in the commit message:

is the above enough?

Bspec index/11740
or CNL:BUG:1929753

> 
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> 
> Regards,
> 
> Tvrtko