[Intel-gfx] Power management test in DP compliance suite

[Navare, Manasi D]

Hi,

I am executing the DP compliance test suite and the only test currently failing with the drm-tip  + my patch  (https://patchwork.freedesktop.org/series/25191/)
Is the power management test (4.4.3) where it expects the source DUT to go into Power state D3 by setting DPCD register 0x600 to 2 as requested by the test GUI and then exit to normal operation by writing 1 to that DPCD register.

I see that in the code intel_dp_sink_dpms() with DPMS_OFF will set that register to 2 and then with DPMS on it sets it to 1, but since that happens only during encoder disable and enable, I am not sure how it will happen through this test.

Any thoughts? Please refer to the section 4.4.3 in the CTS spec.

Regards
Manasi Navare
Graphics Kernel Developer
OTC, Intel Corporation

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