[Intel-gfx] [PATCH v3] drm/i915/cmdparser: Limit clflush to active cachelines

[Mika Kuoppala]

Chris Wilson <chris at chris-wilson.co.uk> writes:

> We only need to clflush those cachelines that we have validated to be
> read by the GPU. Userspace typically fills the batch length in
> correctly, the exceptions tend to be explicit tests within igt.
>
> v2: Use ptr_mask_bits() to make Mika happy
> v3: cmd is not advanced on MI_BBE, so make sure to include an extra
> dword in the clflush.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

I am now very happy.
Reviewed-by: Mika Kuoppala <mika.kuoppala at intel.com>

> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_cmd_parser.c | 25 ++++++++++++++-----------
>  1 file changed, 14 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 21b1cd917d81..7af100f84410 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -1279,11 +1279,17 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine,
>  	 * space. Parsing should be faster in some cases this way.
>  	 */
>  	batch_end = cmd + (batch_len / sizeof(*batch_end));
> -	while (cmd < batch_end) {
> +	do {
>  		u32 length;
>  
> -		if (*cmd == MI_BATCH_BUFFER_END)
> +		if (*cmd == MI_BATCH_BUFFER_END) {
> +			if (needs_clflush_after) {
> +				void *ptr = ptr_mask_bits(shadow_batch_obj->mm.mapping);
> +				drm_clflush_virt_range(ptr,
> +						       (void *)(cmd + 1) - ptr);
> +			}
>  			break;
> +		}
>  
>  		desc = find_cmd(engine, *cmd, desc, &default_desc);
>  		if (!desc) {
> @@ -1323,17 +1329,14 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine,
>  		}
>  
>  		cmd += length;
> -	}
> -
> -	if (cmd >= batch_end) {
> -		DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
> -		ret = -EINVAL;
> -	}
> +		if  (cmd >= batch_end) {
> +			DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
> +			ret = -EINVAL;
> +			break;
> +		}
> +	} while (1);
>  
> -	if (ret == 0 && needs_clflush_after)
> -		drm_clflush_virt_range(shadow_batch_obj->mm.mapping, batch_len);
>  	i915_gem_object_unpin_map(shadow_batch_obj);
> -
>  	return ret;
>  }
>  
> -- 
> 2.11.0