[Intel-gfx] [PATCH v7 06/21] drm/i915/slpc: Lay out SLPC init/enable/disable/cleanup helpers
Sagar Arun Kamble
sagar.a.kamble at intel.com
Wed Mar 22 10:03:39 UTC 2017
SLPC operates based on parameters setup in shared data between
i915 and GuC SLPC. This is to be created/initialized in intel_slpc_init.
>From then onwards i915 can control the SLPC operations by Enabling,
Disabling complete SLPC or changing SLPC parameters. During cleanup
SLPC shared data has to be freed.
With this patch on platforms with SLPC support we call intel_slpc_*()
functions from GuC setup functions and do not use Host rps functions.
With SLPC, intel_enable_gt_powersave will only handle RC6 and ring
frequencies. In the later patch intel_init_gt_powersave will check
if SLPC has started running through shared data and update initial
state that i915 needs like frequency limits.
v1: Return void instead of ignored error code (Paulo)
enable/disable RC6 in SLPC flows (Sagar)
replace HAS_SLPC() use with intel_slpc_enabled()
or intel_slpc_active() (Paulo)
Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
"drm/i915/bxt: Explicitly clear the Turbo control register"
Defer RC6 and SLPC enabling to intel_gen6_powersave_work. (Sagar)
Performance drop with SLPC was happening as ring frequency table
was not programmed when SLPC was enabled. This patch programs ring
frequency table with SLPC. Initial reset of SLPC is based on kernel
parameter as planning to add slpc state in intel_slpc_active. Cleanup
is also based on kernel parameter as SLPC gets disabled in
disable/suspend.(Sagar)
v2: Usage of INTEL_GEN instead of INTEL_INFO->gen (David)
Checkpatch update.
v3: Rebase
v4: Removed reset functions to comply with *_gt_powersave routines.
(Sagar)
v5: Removed intel_slpc_active. Relying on slpc.active for control flows
that are based on SLPC active status in GuC. State setup/cleanup needed
for SLPC is handled using kernel parameter i915.enable_slpc. Moved SLPC
init and enabling to GuC enable path as SLPC in GuC can start doing the
setup post GuC init. Commit message update. (Sagar)
v6: Rearranged function definitions.
v7: Makefile rearrangement. Reducing usage of i915.enable_slpc and relying
mostly on rps.rps_enabled to bypass Host RPS flows. Commit message
update.
Signed-off-by: Tom O'Rourke <Tom.O'Rourke at intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_irq.c | 5 ++++
drivers/gpu/drm/i915/intel_guc_loader.c | 5 ++++
drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++---
drivers/gpu/drm/i915/intel_slpc.c | 42 +++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_slpc.h | 37 +++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_uc.c | 21 +++++++++++++++++
drivers/gpu/drm/i915/intel_uc.h | 3 +++
8 files changed, 134 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
create mode 100644 drivers/gpu/drm/i915/intel_slpc.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 2cf0450..59bbfb5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -60,6 +60,7 @@ i915-y += intel_uc.o \
intel_guc_log.o \
intel_guc_loader.o \
intel_huc.o \
+ intel_slpc.o \
i915_guc_submission.o
# autogenerated null render state
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index cb20c94..38ffc69 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2655,6 +2655,11 @@ static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
set_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags);
wake_up_all(&dev_priv->gpu_error.wait_queue);
+ /*
+ * TODO: Enable SLPC with TDR indication to SLPC in case of
+ * Engine Reset.
+ */
+
do {
/*
* All state reset _must_ be completed before we update the
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 2f270d0..359bd89 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -443,6 +443,11 @@ void intel_guc_fini(struct drm_i915_private *dev_priv)
mutex_lock(&dev_priv->drm.struct_mutex);
i915_guc_submission_disable(dev_priv);
i915_guc_submission_fini(dev_priv);
+ if (i915.enable_slpc) {
+ if (dev_priv->guc.slpc.active)
+ intel_slpc_disable(dev_priv);
+ intel_slpc_cleanup(dev_priv);
+ }
mutex_unlock(&dev_priv->drm.struct_mutex);
obj = fetch_and_zero(&guc_fw->obj);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 18f5f0b..76d98bd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5283,6 +5283,9 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
void gen6_rps_busy(struct drm_i915_private *dev_priv)
{
+ if (!dev_priv->rps.rps_enabled)
+ return;
+
mutex_lock(&dev_priv->rps.hw_lock);
if (dev_priv->rps.rps_enabled) {
u8 freq;
@@ -5311,6 +5314,9 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
void gen6_rps_idle(struct drm_i915_private *dev_priv)
{
+ if (!dev_priv->rps.rps_enabled)
+ return;
+
/* Flush our bottom-half so that it does not race with us
* setting the idle frequency and so that it is bounded by
* our rpm wakeref. And then disable the interrupts to stop any
@@ -6985,6 +6991,12 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
intel_runtime_pm_put(dev_priv);
/* gen6_rps_idle() will be called later to disable interrupts */
+
+ if (dev_priv->guc.slpc.active) {
+ intel_runtime_pm_get(dev_priv);
+ intel_slpc_disable(dev_priv);
+ intel_runtime_pm_put(dev_priv);
+ }
}
void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
@@ -7085,15 +7097,20 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
if (IS_GEN9_BC(dev_priv))
gen6_update_ring_freq(dev_priv);
}
- __intel_enable_gt_powersave(dev_priv);
+
+ if (!i915.enable_slpc)
+ __intel_enable_gt_powersave(dev_priv);
mutex_unlock(&dev_priv->rps.hw_lock);
}
#define GT_POWERSAVE_ENABLED(dev_priv) \
(((INTEL_GEN(dev_priv) >= 9) && \
- (READ_ONCE(dev_priv->rps.rps_enabled) && \
- READ_ONCE(dev_priv->rps.rc6_enabled))) || \
+ ((!i915.enable_slpc && \
+ READ_ONCE(dev_priv->rps.rps_enabled) && \
+ READ_ONCE(dev_priv->rps.rc6_enabled)) || \
+ (i915.enable_slpc && \
+ READ_ONCE(dev_priv->rps.rc6_enabled)))) || \
((INTEL_GEN(dev_priv) < 9) && \
READ_ONCE(dev_priv->rps.rps_enabled)))
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
new file mode 100644
index 0000000..192e777
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include <linux/firmware.h>
+#include "i915_drv.h"
+#include "intel_uc.h"
+
+void intel_slpc_init(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_enable(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_disable(struct drm_i915_private *dev_priv)
+{
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
new file mode 100644
index 0000000..b135a30
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#ifndef _INTEL_SLPC_H_
+#define _INTEL_SLPC_H_
+
+struct intel_slpc {
+ bool active;
+};
+
+/* intel_slpc.c */
+void intel_slpc_init(struct drm_i915_private *dev_priv);
+void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
+void intel_slpc_enable(struct drm_i915_private *dev_priv);
+void intel_slpc_disable(struct drm_i915_private *dev_priv);
+
+#endif
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 8502ead..e811f4f 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -135,6 +135,9 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
ret = i915_guc_submission_init(dev_priv);
if (ret)
goto err;
+
+ if (i915.enable_slpc)
+ intel_slpc_init(dev_priv);
}
/* WaEnableuKernelHeaderValidFix:skl */
@@ -167,6 +170,17 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
goto err_submission;
intel_guc_auth_huc(dev_priv);
+
+ /*
+ * SLPC is enabled by setting up the shared data structure and
+ * sending reset event to GuC SLPC. Initial data is setup in
+ * intel_slpc_init. Here we send the reset event. SLPC enabling
+ * in GuC can happen in parallel in GuC with other initialization
+ * being done in i915.
+ */
+ if (i915.enable_slpc)
+ intel_slpc_enable(dev_priv);
+
if (i915.enable_guc_submission) {
if (i915.guc_log_level >= 0)
gen9_enable_guc_interrupts(dev_priv);
@@ -191,6 +205,11 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
if (i915.enable_guc_submission)
i915_guc_submission_fini(dev_priv);
+ if (i915.enable_slpc) {
+ if (dev_priv->guc.slpc.active)
+ intel_slpc_disable(dev_priv);
+ intel_slpc_cleanup(dev_priv);
+ }
err:
i915_ggtt_disable_guc(dev_priv);
@@ -205,6 +224,8 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
DRM_NOTE("Falling back from GuC submission to execlist mode\n");
}
+ i915.enable_slpc = 0;
+
return ret;
}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 928c214..2e06a23 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -27,6 +27,7 @@
#include "intel_guc_fwif.h"
#include "i915_guc_reg.h"
#include "intel_ringbuffer.h"
+#include "intel_slpc.h"
#include "i915_vma.h"
@@ -174,6 +175,8 @@ struct intel_guc {
uint64_t submissions[I915_NUM_ENGINES];
uint32_t last_seqno[I915_NUM_ENGINES];
+ struct intel_slpc slpc;
+
/* To serialize the intel_guc_send actions */
struct mutex send_mutex;
};
--
1.9.1
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