[Intel-gfx] [PATCH v2 3/4] drm/i915/guc: Simplify programming of GUC_SHIM_CONTROL

[Michal Wajdeczko]

We unconditionally program GUC_SHIM_CONTROL register with
all expected bits, but in case of required workaround we
modify those bits by using additional READ/WRITE calls.
Lets prepare correct value for this register prior to
first register programming.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
Cc: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
 drivers/gpu/drm/i915/i915_guc_reg.h |  7 -------
 drivers/gpu/drm/i915/intel_guc_fw.c | 19 +++++++++++++------
 2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index 35cf991..bc1ae7d 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -102,13 +102,6 @@
 #define   GUC_ENABLE_MIA_CLOCK_GATING		(1<<15)
 #define   GUC_GEN10_SHIM_WC_ENABLE		(1<<21)
 
-#define GUC_SHIM_CONTROL_VALUE	(GUC_DISABLE_SRAM_INIT_TO_ZEROES	| \
-				 GUC_ENABLE_READ_CACHE_LOGIC		| \
-				 GUC_ENABLE_MIA_CACHING			| \
-				 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA	| \
-				 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA	| \
-				 GUC_ENABLE_MIA_CLOCK_GATING)
-
 #define GUC_SEND_INTERRUPT		_MMIO(0xc4c8)
 #define   GUC_SEND_TRIGGER		  (1<<0)
 
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
index 74a61fe..3f013f7 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -100,15 +100,22 @@ int intel_guc_fw_select(struct intel_guc *guc)
 static void guc_prepare_xfer(struct intel_guc *guc)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+	u32 shim_control_value;
 
-	/* Enable MIA caching. GuC clock gating is disabled. */
-	I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
+	/* Expected bits for normal operation */
+	shim_control_value = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
+			     GUC_ENABLE_READ_CACHE_LOGIC |
+			     GUC_ENABLE_MIA_CACHING |
+			     GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
+			     GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
+			     GUC_ENABLE_MIA_CLOCK_GATING;
 
 	/* WaDisableMinuteIaClockGating:bxt */
-	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
-		I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
-					      ~GUC_ENABLE_MIA_CLOCK_GATING));
-	}
+	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
+		shim_control_value &= ~GUC_ENABLE_MIA_CLOCK_GATING;
+
+	/* Must program this register before loading the ucode with DMA */
+	I915_WRITE(GUC_SHIM_CONTROL, shim_control_value);
 
 	/* WaC6DisallowByGfxPause:bxt */
 	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
-- 
2.7.4