[Intel-gfx] [PATCH v2 2/4] drm/i915/guc: Wait for ucode DMA transfer completion

[Sagar Arun Kamble]

On 11/3/2017 3:05 PM, Michal Wajdeczko wrote:
> We silently assumed that DMA transfer will be completed
> within assumed timeout and thus we were waiting only at
> last step for GuC to become ready. Add intermediate wait
> to catch unexpected delays in DMA transfer.
>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Cc: Sagar Arun Kamble <sagar.a.kamble at intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
> ---
>   drivers/gpu/drm/i915/intel_guc_fw.c | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
> index c4f4526..74a61fe 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_guc_fw.c
> @@ -160,6 +160,8 @@ static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma)
>   	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>   	struct intel_uc_fw *guc_fw = &guc->fw;
>   	unsigned long offset;
> +	u32 status;
> +	int ret;
>   
>   	/*
>   	 * The header plus uCode will be copied to WOPCM via DMA, excluding any
> @@ -182,7 +184,12 @@ static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma)
>   	/* Finally start the DMA */
>   	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
>   
> -	return 0;
> +	/* Wait for DMA to finish */
> +	ret = __intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0,
> +					   2, 100, &status);
> +	DRM_DEBUG_DRIVER("GuC DMA status %#x\n", status);
> +
> +	return ret;
>   }
>   
>   /*