[Intel-gfx] [PATCH v2 6/9] drm/i915: expose command stream timestamp frequency to userspace

[Lionel Landwerlin]

On 09/11/17 14:06, Lionel Landwerlin wrote:
>>
>> +    } else if (INTEL_GEN(dev_priv) <= 9) {
>> +        u32 ctc_reg = I915_READ(GEN8_CTC_MODE);
>> +        u64 freq = 0;
>> +
>> +        if ((ctc_reg & GEN8_CTC_SOURCE_PARAMETER_MASK) == 
>> GEN8_CTC_SOURCE_DIVIDE_LOGIC)
>> +            freq = read_timestamp_frequency_from_divide(dev_priv);
>> +        else
>> +            freq = IS_GEN9_LP(dev_priv) ? 19200000 : 24000000;
>> +
>> +        /* Now figure out how the command stream's timestamp register
>> +         * increments from this frequency (it might increment only
>> +         * every few clock cycle).
>> +         */
>> +        freq >>= 3 - ((ctc_reg & GEN8_CTC_SHIFT_PARAMETER_MASK) >>
>> +                  GEN8_CTC_SHIFT_PARAMETER_SHIFT);
> Gen8 documentation is indeed fuzzy. Are we getting 12.5mhz after this 
> shift as doc says it to have 80ns base. 
Forgot to answer that point. Let me check this on BDW again.
But yes, the idea is that we should get 12.5MHz on BDW.
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