[Intel-gfx] [PATCH 03/13] drm/i915/skl: Extract skl_calc_pll_link following bxt, cnl style.

[Rodrigo Vivi]

No functional change. Just spliting the function for
better port clock handling later.

v2: Fix subject and also put link_clock *= 2 back inside
    the new function so we only multiply for DP and avoid
    messing up the HDMI clocks. (Caught by CI).

Cc: Mika Kahola <mika.kahola at intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 71040c3dd6fc..92eabb6cc1ab 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1302,15 +1302,11 @@ static void cnl_ddi_clock_get(struct intel_encoder *encoder,
 	ddi_dotclock_get(pipe_config);
 }
 
-static void skl_ddi_clock_get(struct intel_encoder *encoder,
-				struct intel_crtc_state *pipe_config)
+static int skl_calc_pll_link(struct drm_i915_private *dev_priv,
+			     enum intel_dpll_id pll_id)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	int link_clock = 0;
 	uint32_t dpll_ctl1;
-	enum intel_dpll_id pll_id;
-
-	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
 
 	dpll_ctl1 = I915_READ(DPLL_CTRL1);
 
@@ -1346,7 +1342,18 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder,
 		link_clock *= 2;
 	}
 
-	pipe_config->port_clock = link_clock;
+	return link_clock;
+}
+
+static void skl_ddi_clock_get(struct intel_encoder *encoder,
+			      struct intel_crtc_state *pipe_config)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum intel_dpll_id pll_id;
+
+	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
+
+	pipe_config->port_clock = skl_calc_pll_link(dev_priv, pll_id);
 
 	ddi_dotclock_get(pipe_config);
 }
-- 
2.13.5