[Intel-gfx] [PATCH 02/13] drm/i915/cnl: Extract cnl_calc_pll_link following bxt style.

[Mika Kahola]

On Tue, 2017-10-03 at 00:06 -0700, Rodrigo Vivi wrote:
> No functional change. Just spliting the function for
> better port clock handling later.
> 
> v2: Put link_clock *=2 inside the function only for DP,
>     otherwise we mess up clocks on HDMI. (Caught by CI).
> 
> Cc: Mika Kahola <mika.kahola at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
Reviewed-by: Mika Kahola <mika.kahola at intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 21 ++++++++++++++-------
>  1 file changed, 14 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index b5dd82a0e357..71040c3dd6fc 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1241,15 +1241,11 @@ static void ddi_dotclock_get(struct
> intel_crtc_state *pipe_config)
>  	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
>  }
>  
> -static void cnl_ddi_clock_get(struct intel_encoder *encoder,
> -			      struct intel_crtc_state *pipe_config)
> +static int cnl_calc_pll_link(struct drm_i915_private *dev_priv,
> +			     enum intel_dpll_id pll_id)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
>  	int link_clock = 0;
>  	uint32_t cfgcr0;
> -	enum intel_dpll_id pll_id;
> -
> -	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config-
> >shared_dpll);
>  
>  	cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
>  
> @@ -1290,7 +1286,18 @@ static void cnl_ddi_clock_get(struct
> intel_encoder *encoder,
>  		link_clock *= 2;
>  	}
>  
> -	pipe_config->port_clock = link_clock;
> +	return link_clock;
> +}
> +
> +static void cnl_ddi_clock_get(struct intel_encoder *encoder,
> +			      struct intel_crtc_state *pipe_config)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> +	enum intel_dpll_id pll_id;
> +
> +	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config-
> >shared_dpll);
> +
> +	pipe_config->port_clock = cnl_calc_pll_link(dev_priv,
> pll_id);
>  
>  	ddi_dotclock_get(pipe_config);
>  }
-- 
Mika Kahola - Intel OTC