[Intel-gfx] [PATCH v8 4/5] drm/i915: Do not allocate unused PPAT entries

Wang, Zhi A zhi.a.wang at intel.com
Fri Sep 8 16:30:48 UTC 2017


Check BSpec>Memory Views>Memory Types and Cache Interface>Memory Type [SKL+]>PAT (IA32e) [SKL+]

-----Original Message-----
From: Chris Wilson [mailto:chris at chris-wilson.co.uk] 
Sent: Friday, September 8, 2017 5:27 PM
To: Wang, Zhi A <zhi.a.wang at intel.com>; intel-gfx at lists.freedesktop.org; intel-gvt-dev at lists.freedesktop.org
Cc: joonas.lahtinen at linux.intel.com; zhenyuw at linux.intel.com; Wang, Zhi A <zhi.a.wang at intel.com>; Widawsky, Benjamin <benjamin.widawsky at intel.com>; Vivi, Rodrigo <rodrigo.vivi at intel.com>
Subject: Re: [PATCH v8 4/5] drm/i915: Do not allocate unused PPAT entries

Quoting Zhi Wang (2017-09-08 10:05:52)
> Only PPAT entries 0/2/3/4 are using. Remove extra PPAT entry 
> allocation during initialization.
> 
> v8:
> 
> - Move ppat_index() into i915_gem_gtt.c. (Chris)
> - Change the name of ppat_bits_to_index to ppat_index.
> 
> Cc: Ben Widawsky <benjamin.widawsky at intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Suggested-by: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Signed-off-by: Zhi Wang <zhi.a.wang at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 53 
> +++++++++++++++++++------------------
>  1 file changed, 27 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index d8d2b4a..82cb97b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2979,6 +2979,13 @@ static unsigned int chv_private_pat_match(u8 src, u8 dst)
>                 INTEL_PPAT_PERFECT_MATCH : 0;  }
>  
> +/* PPAT index = 4 * PAT + 2 * PCD + PWT */ static inline unsigned int 
> +ppat_index(unsigned int bits) {
> +       return (4 * !!(bits & _PAGE_PAT) + 2 * !!(bits & _PAGE_PCD)
> +               + !!(bits & _PAGE_PWT));

I'm feeling very dumb, having quickly grepped the bspec for why those bits map to a particular PAT entry. Clue for enlightenment?
-Chris


More information about the Intel-gfx mailing list