[Intel-gfx] [PATCH 5/5] drm/i915/icl: Enable RC6 and RPS in Gen11
Michel Thierry
michel.thierry at intel.com
Thu Apr 5 19:42:15 UTC 2018
On 4/5/2018 7:00 AM, Mika Kuoppala wrote:
> From: Oscar Mateo <oscar.mateo at intel.com>
>
> AFAICT, once the new interrupt is in place, the rest should behave the
> same as Gen10.
>
> v2: Update ring frequencies (Sagar)
> v3: Rebase.
>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> Cc: Sagar Arun Kamble <sagar.a.kamble at intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni at intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo at intel.com>
If it's true that it's the same as Gen10,
Reviewed-by: Michel Thierry <michel.thierry at intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 10 +++++-----
> drivers/gpu/drm/i915/intel_pm.c | 10 ++++------
> 2 files changed, 9 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 1dba2c451255..785b710e4ee4 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1215,20 +1215,20 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
> rp_state_cap >> 16) & 0xff;
> max_freq *= (IS_GEN9_BC(dev_priv) ||
> - IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
> + INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
> intel_gpu_freq(dev_priv, max_freq));
>
> max_freq = (rp_state_cap & 0xff00) >> 8;
> max_freq *= (IS_GEN9_BC(dev_priv) ||
> - IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
> + INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
> intel_gpu_freq(dev_priv, max_freq));
>
> max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
> rp_state_cap >> 0) & 0xff;
> max_freq *= (IS_GEN9_BC(dev_priv) ||
> - IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
> + INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
> intel_gpu_freq(dev_priv, max_freq));
> seq_printf(m, "Max overclocked frequency: %dMHz\n",
> @@ -1811,7 +1811,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
>
> min_gpu_freq = rps->min_freq;
> max_gpu_freq = rps->max_freq;
> - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> + if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
> /* Convert GT frequency to 50 HZ units */
> min_gpu_freq /= GEN9_FREQ_SCALER;
> max_gpu_freq /= GEN9_FREQ_SCALER;
> @@ -1827,7 +1827,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
> seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
> intel_gpu_freq(dev_priv, (gpu_freq *
> (IS_GEN9_BC(dev_priv) ||
> - IS_CANNONLAKE(dev_priv) ?
> + INTEL_GEN(dev_priv) >= 10 ?
> GEN9_FREQ_SCALER : 1))),
> ((ia_freq >> 0) & 0xff) * 100,
> ((ia_freq >> 8) & 0xff) * 100);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a018c9abc2b9..0d25e413ec0b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6572,7 +6572,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
>
> rps->efficient_freq = rps->rp1_freq;
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
> - IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> + IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
> u32 ddcc_status = 0;
>
> if (sandybridge_pcode_read(dev_priv,
> @@ -6585,7 +6585,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
> rps->max_freq);
> }
>
> - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> + if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
> /* Store the frequency values in 16.66 MHZ units, which is
> * the natural hardware unit for SKL
> */
> @@ -6923,7 +6923,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
>
> min_gpu_freq = rps->min_freq;
> max_gpu_freq = rps->max_freq;
> - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> + if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
> /* Convert GT frequency to 50 HZ units */
> min_gpu_freq /= GEN9_FREQ_SCALER;
> max_gpu_freq /= GEN9_FREQ_SCALER;
> @@ -6938,7 +6938,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
> const int diff = max_gpu_freq - gpu_freq;
> unsigned int ia_freq = 0, ring_freq = 0;
>
> - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> + if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
> /*
> * ring_freq = 2 * GT. ring_freq is in 100MHz units
> * No floor required for ring frequency on SKL.
> @@ -8144,8 +8144,6 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
> cherryview_enable_rps(dev_priv);
> } else if (IS_VALLEYVIEW(dev_priv)) {
> valleyview_enable_rps(dev_priv);
> - } else if (WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11)) {
> - /* TODO */
> } else if (INTEL_GEN(dev_priv) >= 9) {
> gen9_enable_rps(dev_priv);
> } else if (IS_BROADWELL(dev_priv)) {
> --
> 2.14.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
More information about the Intel-gfx
mailing list