[Intel-gfx] [PATCH] drm/i915/psr: vbt change for psr
Jani Nikula
jani.nikula at linux.intel.com
Thu Apr 12 09:26:54 UTC 2018
On Wed, 11 Apr 2018, vathsala nagaraju <vathsala.nagaraju at intel.com> wrote:
> From: Vathsala Nagaraju <vathsala.nagaraju at intel.com>
>
> For psr block #9, the vbt description has moved to options [0-3] for
> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
> structure. Since spec does not mention from which VBT version this
> change was added to vbt.bsf file, we cannot depend on bdb->version check
> to change for all the platforms.
>
> There is RCR inplace for GOP team to provide the version number
> to make generic change. Since Kabylake with bdb version 209 is having this
> change, limiting this change to kbl and version 209+ to unblock google.
The point was to move the whole abstraction to intel_bios.c, not just
the version check. To not need any is_tp_time_options field.
I think making platform based restrictions on the vbt fields unless
explicitly specified in the vbt bspec is the wrong thing to do.
BR,
Jani.
>
> bspec 20131
>
> v2: (Jani and Rodrigo)
> move the 165 version check to intel_bios.c
>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> CC: Puthikorn Voravootivat <puthik at chromium.org>
>
> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela at intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju at intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_bios.c | 3 ++
> drivers/gpu/drm/i915/intel_psr.c | 84 ++++++++++++++++++++++++++-------------
> 3 files changed, 61 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5373b17..6aa6d68 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1075,6 +1075,7 @@ struct intel_vbt_data {
> enum psr_lines_to_wait lines_to_wait;
> int tp1_wakeup_time;
> int tp2_tp3_wakeup_time;
> + int is_tp_time_options;
> } psr;
>
> struct {
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index c5c7530..08e82e0 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -659,6 +659,9 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
> return;
> }
>
> + if (bdb->version >= 209 && IS_KABYLAKE(dev_priv))
> + dev_priv->vbt.psr.is_tp_time_options = true;
> +
> psr_table = &psr->psr_table[panel_type];
>
> dev_priv->vbt.psr.full_link = psr_table->full_link;
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 2d53f73..74ed6d0 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -353,24 +353,45 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
> if (dev_priv->psr.link_standby)
> val |= EDP_PSR_LINK_STANDBY;
>
> - if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> - val |= EDP_PSR_TP1_TIME_2500us;
> - else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> - val |= EDP_PSR_TP1_TIME_500us;
> - else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> - val |= EDP_PSR_TP1_TIME_100us;
> - else
> - val |= EDP_PSR_TP1_TIME_0us;
> -
> - if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> - val |= EDP_PSR_TP2_TP3_TIME_2500us;
> - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> - val |= EDP_PSR_TP2_TP3_TIME_500us;
> - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> - val |= EDP_PSR_TP2_TP3_TIME_100us;
> - else
> - val |= EDP_PSR_TP2_TP3_TIME_0us;
> + if (dev_priv->vbt.psr.is_tp_time_options) {
> + if (dev_priv->vbt.psr.tp1_wakeup_time == 0)
> + val |= EDP_PSR_TP1_TIME_500us;
> + else if (dev_priv->vbt.psr.tp1_wakeup_time == 1)
> + val |= EDP_PSR_TP1_TIME_100us;
> + else if (dev_priv->vbt.psr.tp1_wakeup_time == 2)
> + val |= EDP_PSR_TP1_TIME_2500us;
> + else
> + val |= EDP_PSR_TP1_TIME_0us;
> + } else {
> + if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> + val |= EDP_PSR_TP1_TIME_2500us;
> + else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> + val |= EDP_PSR_TP1_TIME_500us;
> + else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> + val |= EDP_PSR_TP1_TIME_100us;
> + else
> + val |= EDP_PSR_TP1_TIME_0us;
> + }
>
> + if (dev_priv->vbt.psr.is_tp_time_options) {
> + if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
> + val |= EDP_PSR_TP2_TP3_TIME_500us;
> + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
> + val |= EDP_PSR_TP2_TP3_TIME_100us;
> + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
> + val |= EDP_PSR_TP2_TP3_TIME_2500us;
> + else
> + val |= EDP_PSR_TP2_TP3_TIME_0us;
> + } else {
> + if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> + val |= EDP_PSR_TP2_TP3_TIME_2500us;
> + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> + val |= EDP_PSR_TP2_TP3_TIME_500us;
> + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> + val |= EDP_PSR_TP2_TP3_TIME_100us;
> + else
> + val |= EDP_PSR_TP2_TP3_TIME_0us;
> + }
> if (intel_dp_source_supports_hbr2(intel_dp) &&
> drm_dp_tps3_supported(intel_dp->dpcd))
> val |= EDP_PSR_TP1_TP3_SEL;
> @@ -405,16 +426,25 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> }
>
> val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
> -
> - if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> - val |= EDP_PSR2_TP2_TIME_2500;
> - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> - val |= EDP_PSR2_TP2_TIME_500;
> - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> - val |= EDP_PSR2_TP2_TIME_100;
> - else
> - val |= EDP_PSR2_TP2_TIME_50;
> -
> + if (dev_priv->vbt.psr.is_tp_time_options) {
> + if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
> + val |= EDP_PSR2_TP2_TIME_500;
> + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
> + val |= EDP_PSR2_TP2_TIME_100;
> + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
> + val |= EDP_PSR2_TP2_TIME_2500;
> + else
> + val |= EDP_PSR2_TP2_TIME_50;
> + } else {
> + if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> + val |= EDP_PSR2_TP2_TIME_2500;
> + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> + val |= EDP_PSR2_TP2_TIME_500;
> + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> + val |= EDP_PSR2_TP2_TIME_100;
> + else
> + val |= EDP_PSR2_TP2_TIME_50;
> + }
> I915_WRITE(EDP_PSR2_CTL, val);
> }
--
Jani Nikula, Intel Open Source Technology Center
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