[Intel-gfx] [PATCH] drm/i915/psr: vbt change for psr

[vathsala nagaraju]

From: Vathsala Nagaraju <vathsala.nagaraju at intel.com>

For psr block #9, the vbt description has moved to options [0-3] for
TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
structure. Since spec does not  mention from which VBT version this
change was added to vbt.bsf file, we cannot depend on bdb->version check
to change for all the platforms.

There is RCR inplace for GOP team to  provide the version number
to make generic change. Since Kabylake with bdb version 209 is having this
change, limiting this change to kbl and version 209+ to unblock google.

Tested on skl(bdb version 203,without options) and
kabylake(bdb version 209,212) having new options.

bspec 20131

v2: (Jani and Rodrigo)
    move the 165 version check to intel_bios.c
v3: Jani
    move the abstraction to intel_bios

Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
CC: Puthikorn Voravootivat <puthik at chromium.org>

Signed-off-by: Maulik V Vaghela <maulik.v.vaghela at intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju at intel.com>
---
 drivers/gpu/drm/i915/intel_bios.c | 40 ++++++++++++++++++++++++++++++++++++---
 drivers/gpu/drm/i915/intel_psr.c  | 26 ++++++++++++-------------
 2 files changed, 50 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 702d3fa..8913dc8 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -646,6 +646,15 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
 	}
 }
 
+static bool
+is_psr_options(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
+{
+	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv))
+		return true;
+	else
+		return false;
+}
+
 static void
 parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 {
@@ -658,7 +667,6 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
 		DRM_DEBUG_KMS("No PSR BDB found.\n");
 		return;
 	}
-
 	psr_table = &psr->psr_table[panel_type];
 
 	dev_priv->vbt.psr.full_link = psr_table->full_link;
@@ -687,8 +695,34 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
 		break;
 	}
 
-	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
-	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
+	/*  new psr options    old decimal value interpretation
+	 *  0 [500 us]         > 1 [500 us ]
+	 *  1 [100 us]         > 0 [100 us ]
+	 *  2 [2.5 ms]         > 5 [2.5 ms ]
+	 *  3 [0   us]         = 0 [0   us ]
+	 */
+	if (!is_psr_options(dev_priv, bdb)) {
+		if (psr_table->tp1_wakeup_time > 5)
+			dev_priv->vbt.psr.tp1_wakeup_time = 2;
+		else if (psr_table->tp1_wakeup_time > 1)
+			dev_priv->vbt.psr.tp1_wakeup_time = 0;
+		else if (psr_table->tp1_wakeup_time > 0)
+			dev_priv->vbt.psr.tp1_wakeup_time = 1;
+		else
+			dev_priv->vbt.psr.tp1_wakeup_time = 3;
+
+		if (psr_table->tp2_tp3_wakeup_time > 5)
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 2;
+		else if (psr_table->tp2_tp3_wakeup_time > 1)
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 0;
+		else if (psr_table->tp1_wakeup_time > 0)
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 1;
+		else
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 3;
+	} else {
+		dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
+		dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
+	}
 }
 
 static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 69a5b27..95658ad 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -353,21 +353,21 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 	if (dev_priv->psr.link_standby)
 		val |= EDP_PSR_LINK_STANDBY;
 
-	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
-		val |= EDP_PSR_TP1_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
+	if (dev_priv->vbt.psr.tp1_wakeup_time == 0)
 		val |= EDP_PSR_TP1_TIME_500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
+	else if (dev_priv->vbt.psr.tp1_wakeup_time == 1)
 		val |= EDP_PSR_TP1_TIME_100us;
+	else if (dev_priv->vbt.psr.tp1_wakeup_time == 2)
+		val |= EDP_PSR_TP1_TIME_2500us;
 	else
 		val |= EDP_PSR_TP1_TIME_0us;
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR_TP2_TP3_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR_TP2_TP3_TIME_500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
+		val |=  EDP_PSR_TP2_TP3_TIME_500us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
 		val |= EDP_PSR_TP2_TP3_TIME_100us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
+		val |= EDP_PSR_TP2_TP3_TIME_2500us;
 	else
 		val |= EDP_PSR_TP2_TP3_TIME_0us;
 
@@ -406,12 +406,12 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
 	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR2_TP2_TIME_2500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
 		val |= EDP_PSR2_TP2_TIME_500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
 		val |= EDP_PSR2_TP2_TIME_100;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
+		val |= EDP_PSR2_TP2_TIME_2500;
 	else
 		val |= EDP_PSR2_TP2_TIME_50;
 
-- 
1.9.1