[Intel-gfx] [PATCH] Revert "drm/i915/icl: WaEnableFloatBlendOptimization"

[Anuj Phogat]

On Mon, Jul 30, 2018 at 5:07 AM Mika Kuoppala <mika.kuoppala at linux.intel.com>
wrote:

> The register for 0xe420 is unable to hold any value, including
> this bit. The documentation is also mixed between having a
> register bit for toggle and having a state command setup
> for it. Apparently the register toggle is deprecated.
>
>   CACHE_MODE_SS is not listed in
a
gfxspecs table
which lists all
user mode
  non-privileged registers. So,
do you think
making any changes
to the register
  from mesa will hold?

> Remove the register toggle as evidence shows it's futile.
>
> The thing remaining is an apology and humble request for
> Mesa folks to resurrect their state setup for this as they
> were on right track from start.
>
> This reverts commit 0bf059f3532bb39c52d917142206a8554fc2f1c5.
>
> Fixes: 0bf059f3532b ("drm/i915/icl: WaEnableFloatBlendOptimization")
> References: HSDES#1406393558
> Cc: Oscar Mateo <oscar.mateo at intel.com>
> Cc: Anuj Phogat <anuj.phogat at gmail.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 3 ---
>  drivers/gpu/drm/i915/intel_workarounds.c | 3 ---
>  2 files changed, 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 7bdc214ffb6e..e0f5999fff07 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2859,9 +2859,6 @@ enum i915_power_well_id {
>  #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE    (1 << 6)
>  #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE   (1 << 1)
>
> -#define GEN10_CACHE_MODE_SS                    _MMIO(0xe420)
> -#define   FLOAT_BLEND_OPTIMIZATION_ENABLE      (1 << 4)
> -
>  #define GEN6_BLITTER_ECOSKPD   _MMIO(0x221d0)
>  #define   GEN6_BLITTER_LOCK_SHIFT                      16
>  #define   GEN6_BLITTER_FBC_NOTIFY                      (1 << 3)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> b/drivers/gpu/drm/i915/intel_workarounds.c
> index f8bb32e974f6..4bcdeaf8d98f 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -508,9 +508,6 @@ static int icl_ctx_workarounds_init(struct
> drm_i915_private *dev_priv)
>                 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>                                   GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
>
> -       /* WaEnableFloatBlendOptimization:icl */
> -       WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS,
> FLOAT_BLEND_OPTIMIZATION_ENABLE);
> -
>         return 0;
>  }
>
> --
> 2.17.1
>
>
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