[Intel-gfx] [PATCH v4 9/9] drm/i915/psr: Check if source supports sink specific SU granularity

[Dhinakaran Pandiyan]

On Mon, 2018-12-03 at 16:34 -0800, José Roberto de Souza wrote:
> According to eDP spec, sink can required specific selective update
> granularity that source must comply.
> Here caching the value if required and checking if source supports
> it.
> 
> v3:
> - Returning the default granularity in case DPCD read
> fails(Dhinakaran)
> - Changed DPCD error message level(Dhinakaran)
> 
> v4:
> - Setting granularity to defaul when granularity read is equal to
> 0(Dhinakaran)
> 
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  1 +
>  drivers/gpu/drm/i915/intel_psr.c | 34 +++++++++++++++++++++++++++++-
> --
>  2 files changed, 32 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 12b8476b09a2..81618af7a5d7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -508,6 +508,7 @@ struct i915_psr {
>  	ktime_t last_exit;
>  	bool sink_not_reliable;
>  	bool irq_aux_error;
> +	u16 su_x_granularity;
>  };
>  
>  enum intel_pch {
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 298c3145212d..cb04d806f456 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -261,6 +261,32 @@ static u8 intel_dp_get_sink_sync_latency(struct
> intel_dp *intel_dp)
>  	return val;
>  }
>  
> +static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp)
> +{
> +	u16 val;
> +	ssize_t r;
> +
> +	/*
> +	 * Returning the default X granularity if granularity not
> required or
> +	 * if DPCD read fails
> +	 */
> +	if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED))
> +		return 4;
> +
> +	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY,
> &val, 2);
> +	if (r != 2)
> +		DRM_DEBUG_KMS("Unable to read
> DP_PSR2_SU_X_GRANULARITY\n");
> +
> +	/*
> +	 * Spec says that if the value read is 0 the default
> granularity should
> +	 * be used instead.
> +	 */
> +	if (r != 2 || val == 0)
> +		val = 4;
> +
> +	return val;
> +}
> +
>  void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *dev_priv =
> @@ -315,6 +341,8 @@ void intel_psr_init_dpcd(struct intel_dp
> *intel_dp)
>  		if (dev_priv->psr.sink_psr2_support) {
>  			dev_priv->psr.colorimetry_support =
>  				intel_dp_get_colorimetry_status(intel_d
> p);
> +			dev_priv->psr.su_x_granularity =
> +				intel_dp_get_su_x_granulartiy(intel_dp)
> ;
>  		}
>  	}
>  }
> @@ -541,9 +569,9 @@ static bool intel_psr2_config_valid(struct
> intel_dp *intel_dp,
>  	 * X coordinate and Y granularity requirements will always be
> met. We
>  	 * only need to validate the SU block width is a multiple of 4.
This comment added in the previous patch is now outdated :) The patch
looks good otherwise,
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>

>  	 */
> -	if (crtc_hdisplay % 4) {
> -		DRM_DEBUG_KMS("PSR2 not enabled, hdisplay(%d) not
> multiple of 4\n",
> -			      crtc_hdisplay);
> +	if (crtc_hdisplay % dev_priv->psr.su_x_granularity) {
> +		DRM_DEBUG_KMS("PSR2 not enabled, hdisplay(%d) not
> multiple of %d\n",
> +			      crtc_hdisplay, dev_priv-
> >psr.su_x_granularity);
>  		return false;
>  	}
>