[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Adding NV12 support (rev12)

[Patchwork]

== Series Details ==

Series: Adding NV12 support (rev12)
URL   : https://patchwork.freedesktop.org/series/28103/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
74d9f6f867c3 drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
98b6c62d8823 drm/i915/skl+: refactor WM calculation for NV12
-:180: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#180: FILE: drivers/gpu/drm/i915/intel_pm.c:4161:
+		 uint16_t *minimum, uint16_t *uv_minimum)

-:198: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#198: FILE: drivers/gpu/drm/i915/intel_pm.c:4194:
+	uint16_t uv_minimum[I915_MAX_PLANES] = {};

-:247: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#247: FILE: drivers/gpu/drm/i915/intel_pm.c:4258:
+		uint16_t plane_blocks, uv_plane_blocks;

total: 0 errors, 0 warnings, 3 checks, 293 lines checked
e7bed55f2300 drm/i915/skl+: add NV12 in skl_format_to_fourcc
dcb163b39ae8 drm/i915/skl+: support verification of DDB HW state for NV12
aff9ae9cb3cc drm/i915/skl+: NV12 related changes for WM
414af2a56424 drm/i915/skl+: pass skl_wm_level struct to wm compute func
549c2d5d8959 drm/i915/skl+: make sure higher latency level has higher wm value
b3ad682adbe1 drm/i915/skl+: nv12 workaround disable WM level 1-7
d97663cbb43c drm/i915/skl: split skl_compute_ddb function
-:113: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#113: FILE: drivers/gpu/drm/i915/intel_pm.c:5141:
+	uint32_t realloc_pipes = pipes_modified(state);

-:132: CHECK: spaces preferred around that '*' (ctx:ExV)
#132: FILE: drivers/gpu/drm/i915/intel_pm.c:5160:
+		*changed = true;
 		^

total: 0 errors, 0 warnings, 2 checks, 194 lines checked
e6098d6cedba drm/i915: Set scaler mode for NV12
-:61: CHECK: Prefer using the BIT macro
#61: FILE: drivers/gpu/drm/i915/i915_reg.h:6736:
+#define PS_SCALER_MODE_PLANAR (1 << 29)

total: 0 errors, 0 warnings, 1 checks, 27 lines checked
ac93c9b078ee drm/i915: Update format_is_yuv() to include NV12
0918e6a75626 drm/i915: Upscale scaler max scale for NV12
-:152: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#152: FILE: drivers/gpu/drm/i915/intel_display.c:12860:
+	uint32_t pixel_format = 0;

total: 0 errors, 0 warnings, 1 checks, 119 lines checked
edeae0e55aa9 drm/i915: Add NV12 as supported format for primary plane
07e8b4d97358 drm/i915: Add NV12 as supported format for sprite plane
e87d0de91200 drm/i915: Add NV12 support to intel_framebuffer_init
-:64: WARNING: line over 80 characters
#64: FILE: drivers/gpu/drm/i915/intel_display.c:14096:
+				      drm_get_format_name(mode_cmd->pixel_format,

-:65: CHECK: Alignment should match open parenthesis
#65: FILE: drivers/gpu/drm/i915/intel_display.c:14097:
+				      drm_get_format_name(mode_cmd->pixel_format,
+				      &format_name));

total: 0 errors, 1 warnings, 1 checks, 14 lines checked
60ae191c5d46 drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
-:27: CHECK: Prefer using the BIT macro
#27: FILE: drivers/gpu/drm/i915/i915_reg.h:6458:
+#define   PLANE_COLOR_YUV601_TO_RGB709		(1 << 17)

total: 0 errors, 0 warnings, 1 checks, 20 lines checked