[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for ICL PLLs, DP/HDMI and misc display

Patchwork patchwork at emeril.freedesktop.org
Thu Feb 22 04:09:51 UTC 2018 

== Series Details ==

Series: ICL PLLs, DP/HDMI and misc display
URL   : https://patchwork.freedesktop.org/series/38737/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
176365bcdda2 drm/i915/icl: add definitions for the ICL PLL registers
-:87: CHECK: Prefer using the BIT macro
#87: FILE: drivers/gpu/drm/i915/i915_reg.h:8982:
+#define   MG_PLL_DIV0_FRACNEN_H				(1 << 30)

-:99: CHECK: Prefer using the BIT macro
#99: FILE: drivers/gpu/drm/i915/i915_reg.h:8994:
+#define   MG_PLL_DIV1_DITHER_DIV_2			(1 << 12)

-:113: CHECK: Prefer using the BIT macro
#113: FILE: drivers/gpu/drm/i915/i915_reg.h:9008:
+#define   MG_PLL_LF_AFCCNTSEL_512			(1 << 20)

-:124: CHECK: Prefer using the BIT macro
#124: FILE: drivers/gpu/drm/i915/i915_reg.h:9019:
+#define   MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32		(1 << 18)

-:125: CHECK: Prefer using the BIT macro
#125: FILE: drivers/gpu/drm/i915/i915_reg.h:9020:
+#define   MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32		(1 << 16)

-:127: CHECK: Prefer using the BIT macro
#127: FILE: drivers/gpu/drm/i915/i915_reg.h:9022:
+#define   MG_PLL_FRAC_LOCK_DCODITHEREN			(1 << 10)

-:128: CHECK: Prefer using the BIT macro
#128: FILE: drivers/gpu/drm/i915/i915_reg.h:9023:
+#define   MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN		(1 << 8)

-:138: CHECK: Prefer using the BIT macro
#138: FILE: drivers/gpu/drm/i915/i915_reg.h:9033:
+#define   MG_PLL_SSC_EN					(1 << 28)

-:142: CHECK: Prefer using the BIT macro
#142: FILE: drivers/gpu/drm/i915/i915_reg.h:9037:
+#define   MG_PLL_SSC_FILEN				(1 << 9)

-:154: CHECK: Prefer using the BIT macro
#154: FILE: drivers/gpu/drm/i915/i915_reg.h:9049:
+#define   MG_PLL_BIAS_BIASCAL_EN			(1 << 15)

-:165: CHECK: Prefer using the BIT macro
#165: FILE: drivers/gpu/drm/i915/i915_reg.h:9060:
+#define   MG_PLL_TDC_COLDST_IREFINT_EN			(1 << 27)

-:167: CHECK: Prefer using the BIT macro
#167: FILE: drivers/gpu/drm/i915/i915_reg.h:9062:
+#define   MG_PLL_TDC_COLDST_COLDSTART			(1 << 16)

-:168: CHECK: Prefer using the BIT macro
#168: FILE: drivers/gpu/drm/i915/i915_reg.h:9063:
+#define   MG_PLL_TDC_TDCCOVCCORR_EN			(1 << 2)

-:178: CHECK: Prefer using the BIT macro
#178: FILE: drivers/gpu/drm/i915/i915_reg.h:9073:
+#define  DPLL_CFGCR0_SSC_ENABLE_ICL	(1 << 25)

total: 0 errors, 0 warnings, 14 checks, 179 lines checked
0212a3eaf876 drm/i915/icl: add basic support for the ICL clocks
-:105: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#105: FILE: drivers/gpu/drm/i915/intel_ddi.c:2151:
+		uint32_t val;

-:291: CHECK: multiple assignments should be avoided
#291: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2436:
+		min = max = icl_port_to_mg_pll_id(port);

-:339: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#339: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2484:
+	uint32_t val;

-:421: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#421: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2566:
+	uint32_t val;

-:472: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#472: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2617:
+	uint32_t val;

-:509: WARNING: quoted string split across lines
#509: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2654:
+	DRM_DEBUG_KMS("dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
+		      "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, "

-:510: WARNING: quoted string split across lines
#510: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2655:
+		      "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, "
+		      "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "

-:511: WARNING: quoted string split across lines
#511: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2656:
+		      "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
+		      "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, "

-:512: WARNING: quoted string split across lines
#512: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2657:
+		      "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, "
+		      "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "

-:513: WARNING: quoted string split across lines
#513: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2658:
+		      "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
+		      "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n",

-:572: CHECK: Please don't use multiple blank lines
#572: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:107:
+
+

-:609: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#609: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:169:
+	uint32_t mg_refclkin_ctl;

-:610: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#610: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:170:
+	uint32_t mg_clktop2_coreclkctl1;

-:611: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#611: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:171:
+	uint32_t mg_clktop2_hsclkctl;

-:612: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#612: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:172:
+	uint32_t mg_pll_div0;

-:613: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#613: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:173:
+	uint32_t mg_pll_div1;

-:614: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#614: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:174:
+	uint32_t mg_pll_lf;

-:615: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#615: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:175:
+	uint32_t mg_pll_frac_lock;

-:616: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#616: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:176:
+	uint32_t mg_pll_ssc;

-:617: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#617: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:177:
+	uint32_t mg_pll_bias;

-:618: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#618: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:178:
+	uint32_t mg_pll_tdc_coldst_bias;

total: 0 errors, 5 warnings, 16 checks, 579 lines checked
394ce70a7d01 drm/i915/icl: compute the combo PHY (DPLL) HDMI registers
-:23: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#23: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2206:
+	uint32_t ref_clock;

-:48: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#48: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2397:
+	uint32_t cfgcr0, cfgcr1;

total: 0 errors, 0 warnings, 2 checks, 52 lines checked
083e316a0ea3 drm/i915/icl: compute the combo PHY (DPLL) DP registers
756e2fb14b68 drm/i915/icl: compute the MG PLL registers
-:30: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#30: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2518:
+				     uint32_t *target_dco_khz,

-:33: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#33: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2521:
+	uint32_t dco_min_freq, dco_max_freq;

-:108: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#108: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2595:
+	uint32_t dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;

-:109: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#109: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2596:
+	uint32_t iref_ndiv, iref_trim, iref_pulse_w;

-:110: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#110: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2597:
+	uint32_t prop_coeff, int_coeff;

-:111: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#111: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2598:
+	uint32_t tdc_targetcnt, feedfwgain;

-:112: CHECK: Prefer kernel type 'u64' over 'uint64_t'
#112: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2599:
+	uint64_t ssc_stepsize, ssc_steplen, ssc_steplog;

-:113: CHECK: Prefer kernel type 'u64' over 'uint64_t'
#113: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2600:
+	uint64_t tmp;

total: 0 errors, 0 warnings, 8 checks, 227 lines checked
96d7a0b68153 drm/i915/icl: Add register definitions for Combo PHY vswing sequences.
-:106: CHECK: Prefer using the BIT macro
#106: FILE: drivers/gpu/drm/i915/i915_reg.h:2097:
+#define   TAP2_DISABLE			(1 << 30)

total: 0 errors, 0 warnings, 1 checks, 69 lines checked
7767df908beb drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake.
-:57: WARNING: line over 80 characters
#57: FILE: drivers/gpu/drm/i915/intel_ddi.c:502:
+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {

-:73: WARNING: line over 80 characters
#73: FILE: drivers/gpu/drm/i915/intel_ddi.c:518:
+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {

-:88: WARNING: line over 80 characters
#88: FILE: drivers/gpu/drm/i915/intel_ddi.c:533:
+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {

-:104: WARNING: line over 80 characters
#104: FILE: drivers/gpu/drm/i915/intel_ddi.c:549:
+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {

-:119: WARNING: line over 80 characters
#119: FILE: drivers/gpu/drm/i915/intel_ddi.c:564:
+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {

-:135: WARNING: line over 80 characters
#135: FILE: drivers/gpu/drm/i915/intel_ddi.c:580:
+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {

total: 0 errors, 6 warnings, 0 checks, 105 lines checked
f68122f9a0b6 drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI
-:67: WARNING: line over 80 characters
#67: FILE: drivers/gpu/drm/i915/intel_ddi.c:861:
+			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);

-:70: WARNING: line over 80 characters
#70: FILE: drivers/gpu/drm/i915/intel_ddi.c:864:
+			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);

-:73: WARNING: line over 80 characters
#73: FILE: drivers/gpu/drm/i915/intel_ddi.c:867:
+			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);

-:82: WARNING: line over 80 characters
#82: FILE: drivers/gpu/drm/i915/intel_ddi.c:876:
+			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);

-:85: WARNING: line over 80 characters
#85: FILE: drivers/gpu/drm/i915/intel_ddi.c:879:
+			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);

-:88: WARNING: line over 80 characters
#88: FILE: drivers/gpu/drm/i915/intel_ddi.c:882:
+			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);

-:117: WARNING: line over 80 characters
#117: FILE: drivers/gpu/drm/i915/intel_ddi.c:2233:
+		DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);

-:162: WARNING: line over 80 characters
#162: FILE: drivers/gpu/drm/i915/intel_ddi.c:2278:
+static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)

total: 0 errors, 8 warnings, 0 checks, 219 lines checked
95188dc60dea drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI
-:36: CHECK: Macro argument reuse 'ln0p1' - possible side-effects?
#36: FILE: drivers/gpu/drm/i915/i915_reg.h:2131:
+#define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
+	_MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))

-:64: CHECK: Prefer using the BIT macro
#64: FILE: drivers/gpu/drm/i915/i915_reg.h:2159:
+#define CRI_USE_FS32			(1 << 5)

-:91: CHECK: Prefer using the BIT macro
#91: FILE: drivers/gpu/drm/i915/i915_reg.h:2186:
+#define CRI_CALCINIT					(1 << 1)

-:148: CHECK: Prefer using the BIT macro
#148: FILE: drivers/gpu/drm/i915/i915_reg.h:2243:
+#define CRI_TXDEEMPH_OVERRIDE_EN			(1 << 22)

total: 0 errors, 0 warnings, 4 checks, 122 lines checked
87682ffe4e06 drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer
a996d61691a8 drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDI
-:57: WARNING: line over 80 characters
#57: FILE: drivers/gpu/drm/i915/intel_ddi.c:2384:
+		DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",

-:77: CHECK: Lines should not end with a '('
#77: FILE: drivers/gpu/drm/i915/intel_ddi.c:2404:
+		val |= CRI_TXDEEMPH_OVERRIDE_17_12(

-:83: CHECK: Lines should not end with a '('
#83: FILE: drivers/gpu/drm/i915/intel_ddi.c:2410:
+		val |= CRI_TXDEEMPH_OVERRIDE_17_12(

-:93: CHECK: Lines should not end with a '('
#93: FILE: drivers/gpu/drm/i915/intel_ddi.c:2420:
+		val |= CRI_TXDEEMPH_OVERRIDE_5_0(

-:95: CHECK: Lines should not end with a '('
#95: FILE: drivers/gpu/drm/i915/intel_ddi.c:2422:
+		       CRI_TXDEEMPH_OVERRIDE_11_6(

-:103: CHECK: Lines should not end with a '('
#103: FILE: drivers/gpu/drm/i915/intel_ddi.c:2430:
+		val |= CRI_TXDEEMPH_OVERRIDE_5_0(

-:105: CHECK: Lines should not end with a '('
#105: FILE: drivers/gpu/drm/i915/intel_ddi.c:2432:
+		       CRI_TXDEEMPH_OVERRIDE_11_6(

total: 0 errors, 1 warnings, 6 checks, 97 lines checked
564b8c7a2810 drm/i915/icl: HPD pin for port F
390f90f94037 drm/i915/icl: Added 5k source scaling support for Gen11 platform
137ca2ea6e11 drm/i915/icl: Calculate link clock using the new registers
f39480af7607 drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL
-:34: CHECK: Prefer using the BIT macro
#34: FILE: drivers/gpu/drm/i915/i915_reg.h:6614:
+#define   PLANE_COLOR_PIPE_GAMMA_ENABLE		(1 << 30) /* Pre-ICL */

-:35: CHECK: Prefer using the BIT macro
#35: FILE: drivers/gpu/drm/i915/i915_reg.h:6615:
+#define   PLANE_COLOR_PIPE_CSC_ENABLE		(1 << 23) /* Pre-ICL */

total: 0 errors, 0 warnings, 2 checks, 27 lines checked
78a0633561af drm/i915/gen11: all the DDI ports on gen 11 support 4 lanes
b154a6a9c427 drm/i915/icl: Fix the DP Max Voltage for ICL

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