[Intel-gfx] [PATCH] drm/i915/psr: Check for power state control capability.

[Rodrigo Vivi]

On Tue, Feb 27, 2018 at 09:55:56AM -0800, Nathan Ciobanu wrote:
> On Mon, Feb 26, 2018 at 07:27:23PM -0800, Dhinakaran Pandiyan wrote:
> > eDP spec says - "If PSR/PSR2 is supported, the SET_POWER_CAPABLE bit in the
> > EDP_GENERAL_CAPABILITY_1 register (DPCD Address 00701h, bit d7) must be set
> > to 1."
> > 
> > Reject PSR on panels without this cap bit set as such panels cannot be
> > controlled via SET_POWER & SET_DP_PWR_VOLTAGE register and the DP source
> > needs to be able to do that for PSR.
> > 
> > Thanks to Nathan for debugging this.
> > 
> > Panel cap checks like this can be done just once, let's fix this
> > when PSR dpcd init movement lands.
> > 
> > Cc: Nathan D Ciobanu <nathan.d.ciobanu at intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
>  Tested-by: Nathan Ciobanu <nathan.d.ciobanu at linux.intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

merging right now. Thanks for the patch, debugs and testing.

> > ---
> >  drivers/gpu/drm/i915/intel_psr.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> > index 89f41d28c44a..e0701b7f87f7 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -405,6 +405,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> >  		return;
> >  	}
> >  
> > +	if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
> > +		DRM_DEBUG_KMS("PSR condition failed: panel lacks power state control\n");
> > +		return;
> > +	}
> > +
> >  	/*
> >  	 * FIXME psr2_support is messed up. It's both computed
> >  	 * dynamically during PSR enable, and extracted from sink
> > -- 
> > 2.14.1
> > 
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> > Intel-gfx at lists.freedesktop.org
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