[Intel-gfx] [PATCH] drm/i915/dp: Add HBR3 rate (8.1 Gbps) to default rates array

[Manasi Navare]

default_rates[] array is a superset of all the link rates supported
by sink devices. DP 1.3 specification adds HBR3 (8.1Gbps) link rate
to the set of link rates supported by sink. This patch adds this rate
to default_rates[] array that gets used to populate the sink_rates[]
array limited by max rate obtained from DP_MAX_LINK_RATE DPCD register.

Cc: Jani Nikula <jani.nikula at linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare at intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2a3b3ae..f0766fb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -103,7 +103,7 @@ static const int skl_rates[] = { 162000, 216000, 270000,
 static const int cnl_rates[] = { 162000, 216000, 270000,
 				 324000, 432000, 540000,
 				 648000, 810000 };
-static const int default_rates[] = { 162000, 270000, 540000 };
+static const int default_rates[] = { 162000, 270000, 540000, 810000 };
 
 /**
  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
-- 
2.7.4