[Intel-gfx] [PATCH] drm/i915/gen9: Disable FBC on planes with a misaligned Y-offset

[Imre Deak]

On Wed, Feb 28, 2018 at 06:05:11PM +0200, Ville Syrjälä wrote:
> On Wed, Feb 28, 2018 at 05:36:56PM +0200, Imre Deak wrote:
> > Enabling FBC on a plane having a Y-offset that isn't dividable by 4 may
> > cause pipe FIFO underruns and flickers, so disable FBC on such a config.
> > 
> > I tried to the followings to work around the issue:
> > - enable each HW work around in ILK_DPFC_CHICKEN
> > - disable each compression algorithm in ILK_DPFC_CONTROL
> > - disable low-power watermarks
> > None of the above got rid of the problem. I haven't found this issue in
> > the Bspec/WA database either.
> > 
> > Besides the igt testcase below (yet to be merged) an easy way to
> > reproduce the issue is to enable a plane with FBC and a plane Y-offset
> > not aligned to 4 and then just enable/disable FBC in a loop, keeping the
> > plane enabled.
> > 
> > I could trigger the problem on BXT/GLK/SKL, so assume for now that it's
> > only present on GEN9.
> > 
> > Cc: Paulo Zanoni <paulo.r.zanoni at intel.com>
> > Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > Testcase: igt/kms_plane/plane-clipping-pipe-A-planes
> > Signed-off-by: Imre Deak <imre.deak at intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_fbc.c | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> > index 38b036c499d9..224c6a795f70 100644
> > --- a/drivers/gpu/drm/i915/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/intel_fbc.c
> > @@ -859,6 +859,17 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
> >  		return false;
> >  	}
> >  
> > +	/*
> > +	 * Work around a problem on GEN9 HW, where enabling FBC on a plane
> > +	 * having a Y offset that isn't dividable by 4 causes FIFO underrun
> > +	 * and screen ficker.
> 
> "divisible", "flicker"
> 
> > +	 */
> > +	if (INTEL_GEN(dev_priv) == 9 &&
> 
> IS_GEN9()?

Ok, will fix those.

> 
> I do wonder about gen10+ however. GLK display pipes/planes did come
> from CNL after all so it seems at least possible tht CNL suffers from
> the same issue.

Hm, right. I thought to enable the WA on CNL in case the same happens in
CI once the igt test is merged. It happens with the testcase somewhat
sporadically though but easy to repro with the FBC on/off method, so
I'll give it a go tomorrow on CNL as well.

I wonder if adding a better testcase doing only FBC on/off would make
sense (without the current delay during FBC enabling).

> 
> The patch seems sensible either way so
> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> > +	    (fbc->state_cache.plane.adjusted_y & 3)) {
> > +		fbc->no_fbc_reason = "plane Y offset is misaligned";
> > +		return false;
> > +	}
> > +
> >  	return true;
> >  }
> >  
> > -- 
> > 2.13.2
> 
> -- 
> Ville Syrjälä
> Intel OTC