[Intel-gfx] [PATCH 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO

[Ville Syrjälä]

On Thu, Jul 12, 2018 at 07:03:58PM +0200, Daniel Vetter wrote:
> On Thu, Jul 12, 2018 at 6:24 PM, Lucas De Marchi
> <lucas.de.marchi at gmail.com> wrote:
> > On Thu, Jul 12, 2018 at 05:04:03PM +0200, Daniel Vetter wrote:
> >> On Mon, Jul 09, 2018 at 09:22:21AM -0700, Lucas De Marchi wrote:
> >> > Instead of defining all registers twice, define just a PCH_GPIO_BASE
> >> > that has the same address as PCH_GPIO_A and use that to calculate all
> >> > the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
> >> > the same thing.
> >> >
> >> > This also rewrites the GMBUS[05] registers since they depend on
> >> > gpio_mmio_base.
> >> >
> >> > v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
> >> >     macro to return a particular gpio address and move the enum out of
> >> >     i915_reg.h (suggested by Jani)
> >> >
> >> > Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/gvt/handlers.c |  2 +-
> >> >  drivers/gpu/drm/i915/i915_reg.h     | 53 +++++++++++++++--------------
> >> >  drivers/gpu/drm/i915/intel_drv.h    | 16 +++++++++
> >> >  drivers/gpu/drm/i915/intel_i2c.c    | 16 ++++-----
> >> >  4 files changed, 52 insertions(+), 35 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> >> > index e39492aaff6c..e25a74fe753b 100644
> >> > --- a/drivers/gpu/drm/i915/gvt/handlers.c
> >> > +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> >> > @@ -2084,7 +2084,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
> >> >
> >> >     MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
> >> >             gmbus_mmio_write);
> >> > -   MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> >> > +   MMIO_F(_MMIO(PCH_GPIO_BASE), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> >> >     MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
> >> >
> >> >     MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> > index 0424e45f88db..f8f71d577613 100644
> >> > --- a/drivers/gpu/drm/i915/i915_reg.h
> >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> > @@ -3088,18 +3088,11 @@ enum i915_power_well_id {
> >> >  /*
> >> >   * GPIO regs
> >> >   */
> >> > -#define GPIOA                      _MMIO(0x5010)
> >> > -#define GPIOB                      _MMIO(0x5014)
> >> > -#define GPIOC                      _MMIO(0x5018)
> >> > -#define GPIOD                      _MMIO(0x501c)
> >> > -#define GPIOE                      _MMIO(0x5020)
> >> > -#define GPIOF                      _MMIO(0x5024)
> >> > -#define GPIOG                      _MMIO(0x5028)
> >> > -#define GPIOH                      _MMIO(0x502c)
> >> > -#define GPIOJ                      _MMIO(0x5034)
> >> > -#define GPIOK                      _MMIO(0x5038)
> >> > -#define GPIOL                      _MMIO(0x503C)
> >> > -#define GPIOM                      _MMIO(0x5040)
> >> > +#define GPIO_OFFSET        0x5010u
> >> > +#define PCH_GPIO_BASE      (0xc0000u + GPIO_OFFSET)
> >> > +#define VLV_GPIO_BASE      (VLV_DISPLAY_BASE + GPIO_OFFSET)
> >>
> >> This is a rather peculiar choice of baseline address. I'd either go with
> >> 0x5000u or 0x0000u (which avoids the need to change all the gmbus macros).
> >
> > I'm all for a round 0x50000 number, however it doesn't match the spec.
> > I don't understand how 0x0 would make sense here. Are you suggesting to
> > embed the GPIO_OFFSET into the GPIO macro and get rid of the GPIO_BASE?
> >
> > #define GPIO_OFFSET     0x5010u
> > /* THESE 2 BELOW COULD USE ANOTHER BETTER NAME */
> > #define PCH_GPIO_BASE   0xc0000u
> > #define VLV_GPIO_BASE   VLV_DISPLAY_BASE
> > #define GPIO(gpio)      _MMIO(dev_priv->gpio_mmio_base + 0x5010 + 4 * (gpio))
> 
> Yeah that's what I had in mind.

I think I like this one the most. Keeps the 0x5010 in the GPIO() macro
so less confusion when looking it up in the spec (except on PCH platforms
perhaps).

Also I would drop the VLV_GPIO_BASE and PCH_GPIO_BASE definitions and
just do gpio_mmio_Base = VLV_DISPLAY_BASE/PCH_DISPLAY_BASE or something
like that.

I've occasionally pondered about some kind of generic south_display_base
thing that could maybe cover all the things that live on the PCH side on
those platforms. But I never bothered to look at all the register offsets
hard enough to figure out whether it'd be actually useful.

-- 
Ville Syrjälä
Intel