[Intel-gfx] [PATCH 02/11] drm/i915/execlists: Reset the CSB head tracking on reset/sanitization

[Tvrtko Ursulin]

On 31/05/2018 19:51, Chris Wilson wrote:
> We can avoid the mmio read of the CSB pointers after reset based on the
> knowledge that the HW always start writing at entry 0 in the CSB buffer.
> We need to reset our CSB head tracking after GPU reset (and on
> sanitization after resume) so that we are expecting to read from entry
> 0.
> 
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>   drivers/gpu/drm/i915/intel_lrc.c | 15 ++++++---------
>   1 file changed, 6 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 517e92c6a70b..e5cf049c18f8 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -965,22 +965,19 @@ static void process_csb(struct intel_engine_cs *engine)
>   			&engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
>   		unsigned int head, tail;
>   
> -		if (unlikely(execlists->csb_use_mmio)) {
> -			buf = (u32 * __force)
> -				(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
> -			execlists->csb_head = -1; /* force mmio read of CSB */
> -		}
> -
>   		/* Clear before reading to catch new interrupts */
>   		clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
>   		smp_mb__after_atomic();
>   
> -		if (unlikely(execlists->csb_head == -1)) { /* after a reset */
> +		if (unlikely(execlists->csb_use_mmio)) {
>   			if (!fw) {
>   				intel_uncore_forcewake_get(i915, execlists->fw_domains);
>   				fw = true;
>   			}
>   
> +			buf = (u32 * __force)
> +				(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
> +
>   			head = readl(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
>   			tail = GEN8_CSB_WRITE_PTR(head);
>   			head = GEN8_CSB_READ_PTR(head);
> @@ -1959,7 +1956,7 @@ static void execlists_reset(struct intel_engine_cs *engine,
>   	spin_unlock(&engine->timeline.lock);
>   
>   	/* Following the reset, we need to reload the CSB read/write pointers */
> -	engine->execlists.csb_head = -1;
> +	engine->execlists.csb_head = GEN8_CSB_ENTRIES - 1;
>   
>   	local_irq_restore(flags);
>   
> @@ -2460,7 +2457,7 @@ static int logical_ring_init(struct intel_engine_cs *engine)
>   			upper_32_bits(ce->lrc_desc);
>   	}
>   
> -	engine->execlists.csb_head = -1;
> +	engine->execlists.csb_head = GEN8_CSB_ENTRIES - 1;
>   
>   	return 0;
>   
> 

Looks OK. Just not that exciting due rarity of the event.

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>

Regards,

Tvrtko