[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/icl: Fix MG PLL setup when refclk is 38.4MHz

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/icl: Fix MG PLL setup when refclk is 38.4MHz
URL   : https://patchwork.freedesktop.org/series/44836/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b74cd00bcd1f drm/i915/icl: Fix MG PLL setup when refclk is 38.4MHz
53a13e6c6e2b drm/i915/icl: Do read-modify-write as needed during MG PLL programming
-:88: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#88: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2957:
+		hw_state->mg_clktop2_hsclkctl &= (

total: 0 errors, 0 warnings, 1 checks, 96 lines checked