[Intel-gfx] [PATCH] drm/i915: Register definitions for DP Phy compiance

[clinton.a.taylor at intel.com]

From: Clint Taylor <clinton.a.taylor at intel.com>

DisplayPort Phy compliance test patterns register definitions.

Signed-off-by: Clint Taylor <clinton.a.taylor at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 95a2e51..91152c9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8702,6 +8702,24 @@ enum skl_power_gate {
 #define  DDI_BUF_BALANCE_LEG_ENABLE	(1 << 31)
 #define DDI_BUF_TRANS_HI(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
 
+/* DDI DP Compliance Control */
+#define DDI_DP_COMP_CTL_A			0x640F0
+#define DDI_DP_COMP_CTL_B			0x641F0
+#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, DDI_DP_COMP_CTL_B)
+#define  DDI_DP_COMP_CTL_ENABLE			(1 << 31)
+#define  DDI_DP_COMP_CTL_D10_2			(0 << 28)
+#define  DDI_DP_COMP_CTL_SCRAMBLED_0		(1 << 28)
+#define  DDI_DP_COMP_CTL_PRBS7			(2 << 28)
+#define  DDI_DP_COMP_CTL_CUSTOM80			(3 << 28)
+#define  DDI_DP_COMP_CTL_HBR2			(4 << 28)
+#define  DDI_DP_COMP_CTL_SCRAMBLED_1		(5 << 28)
+#define  DDI_DP_COMP_CTL_HBR2_RESET		(0xFC << 0)
+
+/* DDI DP Compliance Pattern */
+#define DDI_DP_COMP_PAT_A			0x640f4
+#define DDI_DP_COMP_PAT_B			0x641f4
+#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, DDI_DP_COMP_PAT_B) + (i) * 4) /* 3 dwords */
+
 /* Sideband Interface (SBI) is programmed indirectly, via
  * SBI_ADDR, which contains the register offset; and SBI_DATA,
  * which contains the payload */
-- 
1.9.1