[Intel-gfx] [PATCH 4/6] drm/i915/icl: Enhanced execution list support

Chris Wilson chris at chris-wilson.co.uk
Wed Mar 7 12:45:48 UTC 2018

Quoting Mika Kuoppala (2018-03-02 16:14:59)
> From: Thomas Daniel <thomas.daniel at intel.com>
> Enhanced Execlists is an upgraded version of execlists which supports
> up to 8 ports. The lrcs to be submitted are written to a submit queue
> (the ExecLists Submission Queue - ELSQ), which is then loaded on the
> HW. When writing to the ELSP register, the lrcs are written cyclically
> in the queue from position 0 to position 7. Alternatively, it is
> possible to write directly in the individual positions of the queue
> using the ELSQC registers. To be able to re-use all the existing code
> we're using the latter method and we're currently limiting ourself to
> only using 2 elements.
> v2: Rebase.
> v3: Switch from !IS_GEN11 to GEN < 11 (Daniele Ceraolo Spurio).
> v4: Use the elsq registers instead of elsp. (Daniele Ceraolo Spurio)
> v5: Reword commit, rename regs to be closer to specs, turn off
>     preemption (Daniele), reuse engine->execlists.elsp (Chris)
> v6: use has_logical_ring_elsq to differentiate the new paths
> v7: add preemption support, rename els to submit_reg (Chris)
> v8: save the ctrl register inside the execlists struct, drop CSB
>     handling updates (superseded by preempt_complete_status) (Chris)
> v9: s/drm_i915_gem_request/i915_request (Mika)
> v10: resolved conflict in inject_preempt_context (Mika)
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> Signed-off-by: Thomas Daniel <thomas.daniel at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> (v8)
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
> Signed-off-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>

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