[Intel-gfx] [PATCH] drm/i915/dp: Do not set the eDP link rate/lane count to max

[Manasi Navare]

The panels are generally designed to support only a single
clock and lane configuration, and typically these values
correspond to the native resolution of the panel. But some
panels advertise the MAX_LINK_RATE in DPCD higher than what
is required to support the native resolution.
So optimize and set the link rate and lane count to the
least values required by the panel to support the native
resolution. This will also be an effective power saving
for such eDP panels.

Cc: Jani Nikula <jani.nikula at linux.intel.com>
Cc: Ville Syrjala <ville.syrjala at linux.intel.com>
Cc: Matt Atwood <matthew.s.atwood at intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare at intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8d1d7af..ba1114b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1812,15 +1812,14 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 			bpp = dev_priv->vbt.edp.bpp;
 		}
 
-		/*
-		 * Use the maximum clock and number of lanes the eDP panel
-		 * advertizes being capable of. The panels are generally
-		 * designed to support only a single clock and lane
-		 * configuration, and typically these values correspond to the
-		 * native resolution of the panel.
+		/* The panels are generally designed to support only a single
+		 * clock and lane configuration, and typically these values
+		 * correspond to the native resolution of the panel. But some
+		 * panels advertise higher link rates that might not be required
+		 * for the native resolution of the panel. So use the least
+		 * required link rate/lane count for the panel's native
+		 * resolution.
 		 */
-		min_lane_count = max_lane_count;
-		min_clock = max_clock;
 	}
 
 	for (; bpp >= 6*3; bpp -= 2*3) {
-- 
2.7.4