[Intel-gfx] [PATCH 24/36] drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info
Sagar Arun Kamble
sagar.a.kamble at intel.com
Fri Mar 16 08:10:37 UTC 2018
On 3/14/2018 3:07 PM, Chris Wilson wrote:
> For consistency (and elegance!), add intel_device_info.has_rps.
> The immediate boon is that RPS support is now emitted along the other
> capabilities in the debug log and after errors.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 6 ++++++
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/intel_gt_pm.c | 20 ++++++++++++++++----
> 4 files changed, 25 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7c9cb2f9188b..825a6fd8423b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2559,6 +2559,8 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
> #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
>
> +#define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
> +
> #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
>
> #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 062e91b39085..b2f4c783d8e9 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -235,6 +235,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
> GEN5_FEATURES,
> PLATFORM(INTEL_IRONLAKE),
> .is_mobile = 1, .has_fbc = 1,
> + .has_rps = true,
> };
>
> #define GEN6_FEATURES \
> @@ -246,6 +247,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
> .has_llc = 1, \
> .has_rc6 = 1, \
> .has_rc6p = 1, \
> + .has_rps = true, \
> .has_aliasing_ppgtt = 1, \
> GEN_DEFAULT_PIPEOFFSETS, \
> GEN_DEFAULT_PAGE_SIZES, \
> @@ -290,6 +292,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
> .has_llc = 1, \
> .has_rc6 = 1, \
> .has_rc6p = 1, \
> + .has_rps = true, \
> .has_aliasing_ppgtt = 1, \
> .has_full_ppgtt = 1, \
> GEN_DEFAULT_PIPEOFFSETS, \
> @@ -343,6 +346,7 @@ static const struct intel_device_info intel_valleyview_info = {
> .has_psr = 1,
> .has_runtime_pm = 1,
> .has_rc6 = 1,
> + .has_rps = true,
> .has_gmch_display = 1,
> .has_hotplug = 1,
> .has_aliasing_ppgtt = 1,
> @@ -437,6 +441,7 @@ static const struct intel_device_info intel_cherryview_info = {
> .has_runtime_pm = 1,
> .has_resource_streamer = 1,
> .has_rc6 = 1,
> + .has_rps = true,
> .has_logical_ring_contexts = 1,
> .has_gmch_display = 1,
> .has_aliasing_ppgtt = 1,
> @@ -510,6 +515,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
> .has_csr = 1, \
> .has_resource_streamer = 1, \
> .has_rc6 = 1, \
> + .has_rps = true, \
> .has_dp_mst = 1, \
> .has_logical_ring_contexts = 1, \
> .has_logical_ring_preemption = 1, \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index df014ade1847..9704f4c6cdeb 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -103,6 +103,7 @@ enum intel_platform {
> func(has_psr); \
> func(has_rc6); \
> func(has_rc6p); \
> + func(has_rps); \
> func(has_resource_streamer); \
> func(has_runtime_pm); \
> func(has_snoop); \
> diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c
> index 0cf13e786fe6..21217a5c585a 100644
> --- a/drivers/gpu/drm/i915/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/intel_gt_pm.c
> @@ -710,6 +710,9 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
> {
> struct intel_rps *rps = &dev_priv->gt_pm.rps;
>
> + if (!HAS_RPS(dev_priv))
> + return;
> +
> mutex_lock(&rps->lock);
> if (rps->enabled) {
> u8 freq;
> @@ -740,6 +743,9 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
> {
> struct intel_rps *rps = &dev_priv->gt_pm.rps;
>
> + if (!HAS_RPS(dev_priv))
> + return;
> +
> /*
> * Flush our bottom-half so that it does not race with us
> * setting the idle frequency and so that it is bounded by
> @@ -767,6 +773,9 @@ void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *client)
> unsigned long flags;
> bool boost;
>
> + if (!HAS_RPS(rq->i915))
> + return;
> +
> /*
> * This is intentionally racy! We peek at the state here, then
> * validate inside the RPS worker.
> @@ -909,8 +918,10 @@ static bool sanitize_rc6(struct drm_i915_private *i915)
> struct intel_device_info *info = mkwrite_device_info(i915);
>
> /* Powersaving is controlled by the host when inside a VM */
> - if (intel_vgpu_active(i915))
> + if (intel_vgpu_active(i915)) {
> info->has_rc6 = 0;
> + info->has_rps = 0;
> + }
>
> if (info->has_rc6 &&
> IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(i915)) {
> @@ -2538,7 +2549,7 @@ static void intel_disable_rps(struct drm_i915_private *dev_priv)
> valleyview_disable_rps(dev_priv);
> else if (INTEL_GEN(dev_priv) >= 6)
> gen6_disable_rps(dev_priv);
> - else if (IS_IRONLAKE_M(dev_priv))
> + else if (INTEL_GEN(dev_priv) >= 5)
> ironlake_disable_drps(dev_priv);
>
> dev_priv->gt_pm.rps.enabled = false;
> @@ -2610,7 +2621,7 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
> gen8_enable_rps(dev_priv);
> } else if (INTEL_GEN(dev_priv) >= 6) {
> gen6_enable_rps(dev_priv);
> - } else if (IS_IRONLAKE_M(dev_priv)) {
> + } else if (INTEL_GEN(dev_priv) >= 5) {
> ironlake_enable_drps(dev_priv);
> intel_init_emon(dev_priv);
> }
> @@ -2634,7 +2645,8 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
>
> if (HAS_RC6(dev_priv))
> intel_enable_rc6(dev_priv);
> - intel_enable_rps(dev_priv);
> + if (HAS_RPS(dev_priv))
> + intel_enable_rps(dev_priv);
> if (HAS_LLC(dev_priv))
> intel_enable_llc_pstate(dev_priv);
>
--
Thanks,
Sagar
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