[Intel-gfx] [PATCH 26/36] drm/i915: Reorder GT interface code

[Sagar Arun Kamble]

On 3/14/2018 3:07 PM, Chris Wilson wrote:
> Try to order the intel_gt_pm code to match the order it is used:
>   	init
> 	enable
> 	disable
> 	cleanup
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
> ---
>   drivers/gpu/drm/i915/intel_gt_pm.c | 170 ++++++++++++++++++-------------------
>   drivers/gpu/drm/i915/intel_gt_pm.h |   5 +-
>   2 files changed, 88 insertions(+), 87 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c
> index 42a048dca5bf..feb3bf060f78 100644
> --- a/drivers/gpu/drm/i915/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/intel_gt_pm.c
> @@ -2383,6 +2383,18 @@ static void intel_init_emon(struct drm_i915_private *dev_priv)
>   	dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
>   }
>   
> +void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
> +{
> +	dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */
> +	dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
> +	intel_disable_gt_powersave(dev_priv);
> +
> +	if (INTEL_GEN(dev_priv) < 11)
> +		gen6_reset_rps_interrupts(dev_priv);
> +	else
> +		WARN_ON_ONCE(1);
> +}
> +
>   void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
>   {
>   	struct intel_rps *rps = &dev_priv->gt_pm.rps;
> @@ -2466,91 +2478,6 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
>   	mutex_unlock(&rps->lock);
>   }
>   
> -void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
> -{
> -	if (IS_VALLEYVIEW(dev_priv))
> -		valleyview_cleanup_gt_powersave(dev_priv);
> -
> -	if (!HAS_RC6(dev_priv))
> -		intel_runtime_pm_put(dev_priv);
> -}
> -
> -void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
> -{
> -	dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */
> -	dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
> -	intel_disable_gt_powersave(dev_priv);
> -
> -	if (INTEL_GEN(dev_priv) < 11)
> -		gen6_reset_rps_interrupts(dev_priv);
> -	else
> -		WARN_ON_ONCE(1);
> -}
> -
> -static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
> -{
> -	lockdep_assert_held(&i915->gt_pm.rps.lock);
> -
> -	if (!i915->gt_pm.llc_pstate.enabled)
> -		return;
> -
> -	/* Currently there is no HW configuration to be done to disable. */
> -
> -	i915->gt_pm.llc_pstate.enabled = false;
> -}
> -
> -static void intel_disable_rc6(struct drm_i915_private *dev_priv)
> -{
> -	lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
> -
> -	if (!dev_priv->gt_pm.rc6.enabled)
> -		return;
> -
> -	if (INTEL_GEN(dev_priv) >= 9)
> -		gen9_disable_rc6(dev_priv);
> -	else if (IS_CHERRYVIEW(dev_priv))
> -		cherryview_disable_rc6(dev_priv);
> -	else if (IS_VALLEYVIEW(dev_priv))
> -		valleyview_disable_rc6(dev_priv);
> -	else if (INTEL_GEN(dev_priv) >= 6)
> -		gen6_disable_rc6(dev_priv);
> -
> -	dev_priv->gt_pm.rc6.enabled = false;
> -}
> -
> -static void intel_disable_rps(struct drm_i915_private *dev_priv)
> -{
> -	lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
> -
> -	if (!dev_priv->gt_pm.rps.enabled)
> -		return;
> -
> -	if (INTEL_GEN(dev_priv) >= 9)
> -		gen9_disable_rps(dev_priv);
> -	else if (IS_CHERRYVIEW(dev_priv))
> -		cherryview_disable_rps(dev_priv);
> -	else if (IS_VALLEYVIEW(dev_priv))
> -		valleyview_disable_rps(dev_priv);
> -	else if (INTEL_GEN(dev_priv) >= 6)
> -		gen6_disable_rps(dev_priv);
> -	else if (INTEL_GEN(dev_priv) >= 5)
> -		ironlake_disable_drps(dev_priv);
> -
> -	dev_priv->gt_pm.rps.enabled = false;
> -}
> -
> -void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
> -{
> -	mutex_lock(&dev_priv->gt_pm.rps.lock);
> -
> -	intel_disable_rc6(dev_priv);
> -	intel_disable_rps(dev_priv);
> -	if (HAS_LLC(dev_priv))
> -		intel_disable_llc_pstate(dev_priv);
> -
> -	mutex_unlock(&dev_priv->gt_pm.rps.lock);
> -}
> -
>   static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
>   {
>   	lockdep_assert_held(&i915->gt_pm.rps.lock);
> @@ -2637,6 +2564,79 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
>   	mutex_unlock(&dev_priv->gt_pm.rps.lock);
>   }
>   
> +static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
> +{
> +	lockdep_assert_held(&i915->gt_pm.rps.lock);
> +
> +	if (!i915->gt_pm.llc_pstate.enabled)
> +		return;
> +
> +	/* Currently there is no HW configuration to be done to disable. */
> +
> +	i915->gt_pm.llc_pstate.enabled = false;
> +}
> +
> +static void intel_disable_rc6(struct drm_i915_private *dev_priv)
> +{
> +	lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
> +
> +	if (!dev_priv->gt_pm.rc6.enabled)
> +		return;
> +
> +	if (INTEL_GEN(dev_priv) >= 9)
> +		gen9_disable_rc6(dev_priv);
> +	else if (IS_CHERRYVIEW(dev_priv))
> +		cherryview_disable_rc6(dev_priv);
> +	else if (IS_VALLEYVIEW(dev_priv))
> +		valleyview_disable_rc6(dev_priv);
> +	else if (INTEL_GEN(dev_priv) >= 6)
> +		gen6_disable_rc6(dev_priv);
> +
> +	dev_priv->gt_pm.rc6.enabled = false;
> +}
> +
> +static void intel_disable_rps(struct drm_i915_private *dev_priv)
> +{
> +	lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
> +
> +	if (!dev_priv->gt_pm.rps.enabled)
> +		return;
> +
> +	if (INTEL_GEN(dev_priv) >= 9)
> +		gen9_disable_rps(dev_priv);
> +	else if (IS_CHERRYVIEW(dev_priv))
> +		cherryview_disable_rps(dev_priv);
> +	else if (IS_VALLEYVIEW(dev_priv))
> +		valleyview_disable_rps(dev_priv);
> +	else if (INTEL_GEN(dev_priv) >= 6)
> +		gen6_disable_rps(dev_priv);
> +	else if (INTEL_GEN(dev_priv) >= 5)
> +		ironlake_disable_drps(dev_priv);
> +
> +	dev_priv->gt_pm.rps.enabled = false;
> +}
> +
> +void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
> +{
> +	mutex_lock(&dev_priv->gt_pm.rps.lock);
> +
> +	intel_disable_rc6(dev_priv);
> +	intel_disable_rps(dev_priv);
> +	if (HAS_LLC(dev_priv))
> +		intel_disable_llc_pstate(dev_priv);
> +
> +	mutex_unlock(&dev_priv->gt_pm.rps.lock);
> +}
> +
> +void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
> +{
> +	if (IS_VALLEYVIEW(dev_priv))
> +		valleyview_cleanup_gt_powersave(dev_priv);
> +
> +	if (!HAS_RC6(dev_priv))
> +		intel_runtime_pm_put(dev_priv);
> +}
> +
>   static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
>   {
>   	struct intel_rps *rps = &dev_priv->gt_pm.rps;
> diff --git a/drivers/gpu/drm/i915/intel_gt_pm.h b/drivers/gpu/drm/i915/intel_gt_pm.h
> index c0b3ab5e4046..722325bbb6cc 100644
> --- a/drivers/gpu/drm/i915/intel_gt_pm.h
> +++ b/drivers/gpu/drm/i915/intel_gt_pm.h
> @@ -31,11 +31,12 @@ struct intel_rps_client;
>   void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
>   void intel_gpu_ips_teardown(void);
>   
> -void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
> -void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
>   void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
> +
> +void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
>   void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
>   void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
> +void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
>   
>   void intel_gt_pm_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
>   

-- 
Thanks,
Sagar