[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/12] drm: Add DP PSR2 sink enable bit

[Patchwork]

== Series Details ==

Series: series starting with [01/12] drm: Add DP PSR2 sink enable bit
URL   : https://patchwork.freedesktop.org/series/40521/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
3c6c3ba8cde6 drm: Add DP PSR2 sink enable bit
67ced254aa32 drm: Add DP last received PSR SDP VSC register and bits
f7edbfc94e93 drm/i915/psr: Nuke aux frame sync
307f5aa1e5d2 drm/i915/psr: Tie PSR2 support to Y coordinate requirement
060b501ae2f1 drm/i915/psr/cnl: Enable Y-coordinate support in source
-:26: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#26: FILE: drivers/gpu/drm/i915/i915_reg.h:3895:
+#define   EDP_Y_COORDINATE_VALID	(1<<26) /* GLK and CNL+ */
                                 	  ^

-:27: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#27: FILE: drivers/gpu/drm/i915/i915_reg.h:3896:
+#define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
                                  	  ^

-:35: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#35: FILE: drivers/gpu/drm/i915/i915_reg.h:6903:
+#define  VSC_DATA_SEL_SOFTWARE_CONTROL	(1<<25) /* GLK and CNL+ */
                                       	  ^

total: 0 errors, 0 warnings, 3 checks, 43 lines checked
6659daf1e4d9 drm/i915/psr: Do not override PSR2 sink support
83a99661c27d drm/i915/psr: Use PSR2 macro for PSR2
ebf449282d26 drm/i915/psr: Cache sink synchronization latency
70148c4aea67 drm/i915/psr: Set DPCD PSR2 enable bit when needed
0f9a21c67357 drm/i915/debugfs: Print sink PSR state and debug info
5fda9554238b drm/i915/debugfs: Print information about what caused a PSR exit
ff1a90ddf554 drm/i915/debugfs: Print how many blocks were sent in a selective update