[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/11] drm/i915/execlists: Avoid kicking the submission too early for rescheduling

Patchwork patchwork at emeril.freedesktop.org
Mon Mar 26 12:08:55 UTC 2018


== Series Details ==

Series: series starting with [01/11] drm/i915/execlists: Avoid kicking the submission too early for rescheduling
URL   : https://patchwork.freedesktop.org/series/40665/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
6cd6e46a6275 drm/i915/execlists: Avoid kicking the submission too early for rescheduling
-:19: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#19: 
References: f6322eddaff7 ("drm/i915/preemption: Allow preemption between submission ports")

-:19: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit f6322eddaff7 ("drm/i915/preemption: Allow preemption between submission ports")'
#19: 
References: f6322eddaff7 ("drm/i915/preemption: Allow preemption between submission ports")

total: 1 errors, 1 warnings, 0 checks, 30 lines checked
571ee98c9870 drm/i915/execlists: Clear user-active flag on preemption completion
d3c6c6e49941 drm/i915: Include submission tasklet state in engine dump
84c375a58791 drm/i915/execlists: Refactor out complete_preempt_context()
e0fa2379926b drm/i915: Move engine reset prepare/finish to backends
b9c4fb9ea980 drm/i915: Split execlists/guc reset prepartions
17bce80a463b drm/i915/execlists: Flush pending preemption events during reset
-:91: WARNING:LONG_LINE: line over 100 characters
#91: FILE: drivers/gpu/drm/i915/intel_lrc.c:907:
+			head = readl(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));

-:108: WARNING:LONG_LINE: line over 100 characters
#108: FILE: drivers/gpu/drm/i915/intel_lrc.c:921:
+			  head, GEN8_CSB_READ_PTR(readl(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)))), fw ? "" : "?",

-:109: WARNING:LONG_LINE: line over 100 characters
#109: FILE: drivers/gpu/drm/i915/intel_lrc.c:922:
+			  tail, GEN8_CSB_WRITE_PTR(readl(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)))), fw ? "" : "?");

total: 0 errors, 3 warnings, 0 checks, 200 lines checked
ebbe79e61164 drm/i915/execlists: Force preemption via reset on timeout
1992a69b17b3 drm/i915/preemption: Select timeout when scheduling
b72df86f0c84 drm/i915: Use a preemption timeout to enforce interactivity
ae480c117350 drm/i915: Allow user control over preempt timeout on the important context



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