[Intel-gfx] [PATCH 03/11] drm/i915: Include submission tasklet state in engine dump

[Mika Kuoppala]

Chris Wilson <chris at chris-wilson.co.uk> writes:

> For the off-chance we have an interrupt posted and haven't processed the
> CSB.
>
> v2: Include tasklet enable/disable state for good measure.

Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>

>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index de09fa42a509..12486d8f534b 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1859,12 +1859,15 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
>  		ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
>  		read = GEN8_CSB_READ_PTR(ptr);
>  		write = GEN8_CSB_WRITE_PTR(ptr);
> -		drm_printf(m, "\tExeclist CSB read %d [%d cached], write %d [%d from hws], interrupt posted? %s\n",
> +		drm_printf(m, "\tExeclist CSB read %d [%d cached], write %d [%d from hws], interrupt posted? %s, tasklet queued? %s (%s)\n",
>  			   read, execlists->csb_head,
>  			   write,
>  			   intel_read_status_page(engine, intel_hws_csb_write_index(engine->i915)),
>  			   yesno(test_bit(ENGINE_IRQ_EXECLIST,
> -					  &engine->irq_posted)));
> +					  &engine->irq_posted)),
> +			   yesno(test_bit(TASKLET_STATE_SCHED,
> +					  &engine->execlists.tasklet.state)),
> +			   enableddisabled(!atomic_read(&engine->execlists.tasklet.count)));
>  		if (read >= GEN8_CSB_ENTRIES)
>  			read = 0;
>  		if (write >= GEN8_CSB_ENTRIES)
> -- 
> 2.16.3
>
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